Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

11.5.3. Lightweight HPS-to-FPGA Bridge

This bridge has the same function as the H2F bridge. Crucially though, the lightweight H2F bridge is meant for a narrower use case involving simple peripherals on the FPGA with strongly ordered single transactions. Customers can use this bridge to program the configuration registers for FPGA IPs.

The LWH2F bridge sits in between the AXI-4 32-bit NIU of the PSS NOC and the boundary of the HPS. The bridge contains register slice. On the PSS NOC, 1 dedicated target NIU of 32-bit is instantiated. The block diagram for the lightweight H2F bridge.

Figure 289. LWH2F Bridge Block Diagram

The following table lists the bridge signals for the LWH2F Bridge bridge.

Table 340.  LWH2F Bridge Signals
Name Direction Description
lwhps2fpga_axi_clock Input

Clock from a single source in the FPGA.

lwhps2fpga_axi_reset Input

Async active high reset to the bridge.

Note: h2f_reset signal must be connected to lwhps2fpga_axi_reset signal for proper bridge operation.

The following table shows the properties of the LWH2F bridge.

Table 341.  LWH2F Bridge Properties
Bridge Property Value
Protocol AXI-4
Clock lwhps2fpga_axi_clock (from FPGA)
Data Width 32
Address Width 29
ID Width 4
A*Region Width 0
A*Len Width 8
A*QoS Width 0
FIXED Burst Yes
Exclusive Support Yes (external monitor)
Min Narrow Burst Size 1 byte
Max Wrap Burst Size 64 bytes
nPendingTrans (Issuance/Acceptance) 16
nPendingOrderID 16
Ready Latency requirement Yes