Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.10.5.1. Interface to HPS I/O

Table 269.  SPI Master Interface Pins

Signal Name

Signal Width

Direction

Description

CLK

1

Out

Serial clock output from the SPI master

MOSI

1

Out

Transmit data line for the SPI master

MISO

1

In

Receive data line for the SPI master

SS0_N

1

Out

Slave Select 0: Slave select signal from SPI master

SS1_N

1

Out

Slave Select 1: Slave select signal from SPI master

Table 270.  SPI Slave Interface Pins

Signal Name

Signal Width

Direction

Description

CLK

1

In

Serial clock input to the SPI slave

MOSI

1

In

Receive data line for the SPI slave

MISO

1

Out

Transmit data line for the SPI slave

SS0_N

1

In

Slave select input to the SPI slave