Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.5.7.4. Handling FIFO DQS Overflow and Underrun

Previously was described the combo PHY read path. To describe the DQS overflow and underrun condition, the read data flow can be simplified as shown in the figure below. In the figure, data from the NAND Flash are written to the data FIFO with the delayed DQS (write strobe) signal. The PHY returns data on the DFI interface based on the delayed rddata_en signal.

Figure 167. Data Flow Diagram of Read Path

The dqs_overflow signal is set as an indication that the data FIFO was filled completely by data from the Flash device during the read operation. The delay in the enable read signal (delayed rddata_en) can be configured by the rd_del_sel field in the phy_gate_lpbk_ctrl_reg register. If this value is too high, the consumption of data from FIFO might not start before the FIFO gets full and the overflow occurs. To prevent this scenario, reduce the value of the rd_del_sel field.

The dqs_underrun signal is set to indicate that the data FIFO is empty. This may occur in two scenarios:

  • The delayed DQS signal was not propagated to the data FIFO (due to a Flash device error or DQS Gate configuration). This can be fixed by reducing the value of the gate_cfg field in the phy_gate_lpbk_ctrl_reg register.
  • The delayed DQS signal arrived in the FIFO too late. This can be fixed by increasing the value of the rd_del_sel field in the phy_gate_lpbk_ctrl_reg register.

The DQS overflow/underflow applies for the DQ path and the CMD path. The status of these signals can be observed in the phy_obs_reg_0 register as described in the following table.

Table 233.  phy_obs_reg_0 Signal Status
Description DQ Read Path CMD Read Path
DQS overflow dqs_overflow dqs_cmd_overflow
DQS underflow dqs_underrun dqs_cmd_underrun