Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

7.6.10. GPIO Debounce Clock Group

The GPIO debounce clock tree contains a ping-pong counter, a 16-bit divider and a clock gate, as shown in the following diagram.

Figure 265. GPIO Debounce Clock Group Block Diagram

The following table shows the registers used to program the clocks.

Table 310.  Programming Clock Registers
Clock Name *.src

*.cnt

(n+1 divider)

*.div (2^n divider) Clock Gate (enable)
gpio_db_clk

ctlgrp.gpiodbctr.src

= 0 (Main_PLL_C3)

= 1 (Peri_PLL_C1)

ctlgrp.gpiodbctr.cnt

perpllgrp.gpiodiv.gpiodbclk 34

perpllgrp.en.gpiodben
34 perpllgrp.gpiodiv.gpiodbclk is actually a n+1 divider, and not a 2^n divider. A divide by 1 value (perpllgrp.gpiodiv.gpiodbclk = 0) is not supported and may produce unpredictable results.