Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

6.4.1.3. EMAC

You can program the tsn_global.ptp_clock_sel register to select either tsn_ptp_clk from the clock manager or f2s_ptp_ref_clk from the FPGA fabric as the source of the IEEE 1588 reference clock for each EMAC.

You can program the system manager's tsn*_ace registers to control the EMAC's AWSID and ARSID signals.

Note: Register bits must be accessed only when the master interface is guaranteed to be in an inactive state.

The tsn*.phy_intf_sel bit is programmed to select between a GMII and RGMII interface when the peripheral is released from reset. The EMAC controllers only support internal timestamp reference.