Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public

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4.3.4.3.2.5. Interrupt Interfaces for TBU

Each TBU includes an interrupt interface that provides global, per-context and performance interrupts.

Table 87.  TBU Interrupt signal connection

Signal Name

IO

Connectivity

Description

ras_irpt

O

Connected to GIC

RAS Interrupt

pmu_irpt

O

Connected to GIC

PMU Interrupt