Visible to Intel only — GUID: sez1679283842988
Ixiasoft
Visible to Intel only — GUID: sez1679283842988
Ixiasoft
15.5.2.5. Trace Port Interface Unit (TPIU)
The TPIU’s trace port output connectivity provides connectivity to support using either HPS or FPGA GPIO as the destination for the trace port pins. Use the trace port repeaters to ensure timing to the IO matches Arm* 's trace port requirements.
The TPIU is a bridge between on-chip trace sources and an off-chip trace port. The TPIU receives trace data from the ATB bus slave and drives the trace data to a trace port analyzer.
The trace output is routed to a 32-bit interface to the FPGA fabric. The trace data sent to the FPGA fabric can be transported off-chip using available serializer/deserializer (SERDES) resources in the FPGA. The following table shows the HPS trace signals.
Signal | Description |
---|---|
h2f_tpiu_clk | TPIU trace clock output. TPIU generates this clock by dividing cs_atclk by 2. Supported frequency: 200/100/50/25/12.5 MHz |
h2f_tpiu_data[15:0] | TPIU trace clock output. TPIU generates this clock by dividing cs_atclk by 2. Supported frequencies: 200/100/50/25/12.5 MHz |