Visible to Intel only — GUID: iuj1708452489856
Ixiasoft
Visible to Intel only — GUID: iuj1708452489856
Ixiasoft
8.7.5.1. FPGA Boot First
If the FPGA First configuration has been selected, and after a Power-On-Reset (POR), then the SDM drives the HPS_COLD_nRESET signal to output low. At this point, referring to the Agilex™ 5 Configuration User Guide, the bitstream configuration file containing the FSBL must be resent to the SDM using the same interface that the MSEL[2:0] pins specified during POR. After the bitstream has been received, and after the FPGA is in User Mode, the SDM releases the HPS from reset, and the HPS_COLD_nRESET signal is configured as an input and can be pulled high by the external pull-up resister. The following figures show the FPGA boot first behavior.
If the FPGA First configuration has been selected, and after nCONFIG has been asserted, then the SDM will drive the HPS_COLD_nRESET signal to output low. At this point, referring to the Agilex™ 5 Configuration User Guide, the bitstream has been received, and after the FPGA is in User Mode, the SDM releases the HPS from reset, and the HPS_COLD_nRESET signal is configured as an input and can be pulled high by the external pull-up resistor.