Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

2. Introduction to the Hard Processor System

The Agilex™ 5 system-on-a-chip (SoC) is composed of two distinct portions: a dual-core Arm* Cortex* -A76, a dual-core Arm* Cortex* -A55 hard processor system (HPS) and a FPGA. The HPS architecture integrates a wide set of peripherals that reduces board size and increases performance within a system.

The HPS communicates outside of the SoC through the following types of interfaces:
  • Dedicated I/O interfaces
  • FPGA fabric interfaces
  • FPGA secure device manager (SDM) interfaces
  • Interface to DDR memory
  • USB 3.1 interface to PHY
Key modules in the HPS include:
  • Dual-core Arm* Cortex* -A76 and dual-core Arm* Cortex* -A55 processor
  • Level 3 (L3) interconnect
  • Cache coherency unit (CCU)
  • System memory management unit (SMMU)
  • Multi-port front end (MPFE) subsystem, consisting of the hard memory controller adaptor and interface to the CCU interconnect
  • DMA controller
  • On-chip RAM
  • Debug components
  • PLLs
  • Flash memory controllers
  • Support peripherals
  • Interface peripherals

The HPS incorporates third-party intellectual property (IP) from several vendors. Refer to HPS IP Revisions for details.

The FPGA portion of the device contains:
  • FPGA fabric
  • PLLs
  • User I/Os
  • Hard memory controllers
  • Secure Device Manager (SDM)

The HPS and FPGA portions of the device each have their own pins. The HPS has dedicated I/O pins. You can route some of the HPS peripherals to the FPGA fabric to use the FPGA I/O.

You can boot the HPS from a power-on reset in one of two ways:
  • FPGA configures first and then optionally boots the HPS (also called FPGA configuration first).
  • HPS boots first and then configures the FPGA (called HPS boot first).

For more information, refer to the Booting and Configuration appendix.