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Ixiasoft
Visible to Intel only — GUID: obd1666889743586
Ixiasoft
2. Introduction to the Hard Processor System
The Agilex™ 5 system-on-a-chip (SoC) is composed of two distinct portions: a dual-core Arm* Cortex* -A76, a dual-core Arm* Cortex* -A55 hard processor system (HPS) and a FPGA. The HPS architecture integrates a wide set of peripherals that reduces board size and increases performance within a system.
- Dedicated I/O interfaces
- FPGA fabric interfaces
- FPGA secure device manager (SDM) interfaces
- Interface to DDR memory
- USB 3.1 interface to PHY
- Dual-core Arm* Cortex* -A76 and dual-core Arm* Cortex* -A55 processor
- Level 3 (L3) interconnect
- Cache coherency unit (CCU)
- System memory management unit (SMMU)
- Multi-port front end (MPFE) subsystem, consisting of the hard memory controller adaptor and interface to the CCU interconnect
- DMA controller
- On-chip RAM
- Debug components
- PLLs
- Flash memory controllers
- Support peripherals
- Interface peripherals
The HPS incorporates third-party intellectual property (IP) from several vendors. Refer to HPS IP Revisions for details.
- FPGA fabric
- PLLs
- User I/Os
- Hard memory controllers
- Secure Device Manager (SDM)
The HPS and FPGA portions of the device each have their own pins. The HPS has dedicated I/O pins. You can route some of the HPS peripherals to the FPGA fabric to use the FPGA I/O.
- FPGA configures first and then optionally boots the HPS (also called FPGA configuration first).
- HPS boots first and then configures the FPGA (called HPS boot first).
For more information, refer to the Booting and Configuration appendix.