Visible to Intel only — GUID: wwf1672351110349
Ixiasoft
Visible to Intel only — GUID: wwf1672351110349
Ixiasoft
3.1. MPU Differences Among Intel SoC Device Families
MPU Feature | Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC, Intel® Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC |
---|---|---|---|---|
CPU | Single/Dual Cortex* -A9 | Dual Cortex* -A9 | Quad Cortex* -A53 | Dual Cortex* -A76 and dual Cortex* -A55 with DSU |
Maximum frequency (MHZ) | Cyclone® V SoC: 925 Arria® V SoC: 1050 |
1500 | Stratix® 10 SoC: 1350 Intel® Agilex™ 7 F-Series/I-Series/M-Series: 1500 |
Cortex* -A76: 1800 Cortex* -A55: 1500 |
Core revision | r3p0 | r4p1 | r0p4 | Cortex* -A76: r4p1 Cortex* -A55: r2p0 DSU: r4p0 |
L1 instruction cache | 32 KB per core | 32 KB per core | 32 KB per core | Cortex* -A76: 64 KB per core Cortex* -A55: 32 KB per core |
L1 data cache | 32 KB per core | 32 KB per core | 32 KB per core | Cortex* -A76: 64 KB per core Cortex* -A55: 32 KB per core |
L2 cache | 512 KB shared | 512 KB shared | 1 MB shared | Cortex* -A76: 256 KB per core Cortex* -A55: 128 KB per core |
L3 cache | No | No | No | 2 MB shared |
System level cache coherency | Implemented by accelerator coherency port (ACP) | Implemented by ACP | Implemented by cache coherency unit (CCU) | Implemented by cache coherency unit (CCU) |
L1 data cache error checking | Parity 7 | Parity7 | ECC 8 | ECC 9 |
L1 instruction cache error checking | Parity7 | Parity7 | Parity7 | Parity7 |
L2 cache error checking | ECC9 | ECC9 | ECC9 | ECC9 |
Translation lookaside buffer (TLB) error checking | Parity7 | Parity7 | Parity7 | Parity7 |