Visible to Intel only — GUID: jfo1684438640462
Ixiasoft
Visible to Intel only — GUID: jfo1684438640462
Ixiasoft
5.3.6.4.3.2. Last Operation Status
The NAND Flash controller obtains the status of the last operation executed on a specific thread. The thread is selected using the cmd_status_ptr (0x0010) register and the status information can be retrieved from the cmd_status (0x0014) register. The status information is valid only if the Complete bit is set. After a new command is triggered in the selected thread, the Complete bit is cleared and then other bits in the status register are invalid until the Complete bit is asserted again.
The following table shows layout and fields description for the status register in the PIO operation mode.
Bit | Name | Description |
---|---|---|
63:56 | pl_ecc_err |
Each bit of this field provides ECC error status for the corresponding plane. |
55:48 | pl_device_error |
Each bit of this field provides device error status for the corresponding plane. If the pl_status_en bit in the multiplane_config (0x0434) register is cleared, then all bits corresponding to planes present inside devices are set. |
47:32 | Reserved | Reserved |
31:24 | Error Index | If the Fail bit is set, this field indicates the operation index number where the first error was detected. Operations are numbered from zero. This field is not updated when source of error is transfer on the system bus — in this case only the Bus Error bit is set. |
23:21 | Reserved | Reserved |
20 | prot_err | When set, this bit indicates that a program operation tried to modify a protected area. |
19 | di_ctx_err | When set, this bit indicates that a parity error was detected on the data bus during access to the context memory. Additionally, this bit is set when parity error is detected during access to the remap memory. |
18 | di_dsc_err | When set, this bit indicates that parity error was detected on the data bus during access to the system bus. |
17 | di_dat_err | When set, this bit indicates that data integrity error was detected in the data path. |
16 | Bus error | When set, this bit indicates that the controller got an error response on the system bus. |
15 | Complete | When set, this bit indicates that the controller has updated status information and the operation is complete. This bit must be set even if the operation ended as a failure. |
14 | Fail | When set, this bit indicates that the operation failed to complete successfully. |
13 | DQS Error | Incorrect DQS pulses number was detected during the data read operation. This is information from the PHY that either the DQS strobe did not appear during read (for example, device is not connected to the controller) or rd_del_sel signal value is wrong (field in the phy_gate_lpbk_ctrl_reg) and data read from Flash device are corrupted and read fifo pointers in the PHY are misaligned. The dll_rst_n or rst_n signals clear dfi_dqs_underrun/dfi_dqs_overflow flags in the PHY and clears all PHY read data pointers. One of these is required by the PHY before continuing to work after dfi_dqs_underrun/dfi_dqs_overflow assertion. |
12 | Device error | Device error was detected during read status operation in any of the device planes. |
11 | Erased Page | When set, this bit indicates that the controller detected an erased page in the read transaction. The detection of erased page is based on the number of 0s in a page. If the number of 0s in a page being read is less than the value on the erase_det_lvl field of the ecc_config_1 (0x042c) register, an erased page is inferred and no uncorrectable error is flagged for that page. If ECC is disabled, the erased_page interrupt must be set as explained above. If ECC is enabled, in addition to the above condition, only when the ECC logic detects no errors or correctable error pattern for that page will the erased_page interrupt be flagged. If the ECC logic detects an uncorrectable error page, this erased page interrupt is not set. This flag does not contribute to the Fail flag. |
10 | Reserved | Reserved |
9:2 | Max Error | For the Flash read command, this field indicates the maximum amount of correction applied to one ECC sector. This field is of significance only if the read transaction resulted in correctable errors. If no errors are found, this field is zero. |
1 | ecc_err | Uncorrectable ECC error was detected for the any of the device planes. |
0 | Command Error | This bit is set when a programmed command sequence cannot be executed because of incorrect controller or command configuration. This bit is not set when unknown commands are programmed to the command registers. Error sources for this bit are described in Descriptor/Command Error section. |