Visible to Intel only — GUID: qqi1688765640903
Ixiasoft
Visible to Intel only — GUID: qqi1688765640903
Ixiasoft
12.3.1.3.1. HPS GMII to RGMII Adapter Intel FPGA IP
You can implement the HPS GMII to RGMII Adapter Intel FPGA IP into FPGA fabric to convert the GMII interface of the Ethernet controller in the hard processor system (HPS) to RGMII interface via FPGA IO connectivity. By default, the HPS Ethernet controller was configured as RGMII interface routed to HPS I/O but you have the option to configure EMAC interface to expose as GMII interface in FPGA fabric, and connect to FPGA I/O.
Intel offers HPS GMII-to-RGMII Adapter Intel FPGA IP, as the RTL adaptation solution for you to interface EMAC to an external RGMII PHY through the FPGA logic.
Features
The following features are supported by the HPS GMII to RGMII Adapter Intel FPGA IP.
- Performs GMII interface to RGMII interface conversion
- Supports tri-speed (10/100/1000 Mbps) operation
- Supports dynamic speed switching
- Supports generation time option to enable pipeline registers for the transmit and receive paths
You can refer to the RGMII Design Guidelines on guidelines to meet desired RGMII clock skew relationship.
Data Path
For transmit path, the GMII data goes through the transmit pipeline register stage before going into the RGMII Output Standard Function (RGMII_O SF) Converter Block. The pipeline logic is optional and you can enabled or disabled during IP generation time.
For receive path, the GMII data right after the RGMII Input Standard Function (RGMII_I SF) Converter Block goes through the receive pipeline register stage then directly to the HPS EMAC GMII interface. Similarly, you can enable or disable this pipeline logic during IP generation time.
The RGMII_I/O SF converter block manages single data rate to double data rate conversion and vice-versa. The Agilex™ 5 FPGA HVIO component is used to perform this task. This block also decodes collision and carrier sense condition through In-Band status detection.
Signal Interfaces
The following table provides the signal interfaces information.
Signal Name | Direction | Type | Description |
---|---|---|---|
clk | Input | Clock | Peripheral clock source |
rst_n | Input | Reset | Active low peripheral asynchronous reset source. This signal is expected to be asynchronously asserted and synchronously de-asserted associated to the peri_clock. Synchronous de-assertion must be provided external to this core. |
pll_25m_clock | Input | Clock | 25 MHz input clock from FPGA PLL |
pll_2_5m_clock | Input | Clock | 2.5 MHz input clock from FPGA PLL |
pll_125m_tx_clock | Input | Clock | 125 MHz input clock from FPGA PLL |
locked_pll_250m_tx | Input | Clock | Plase-locked indicator for 250 MHz input clock from FPGA PLL |
pll_250m_tx_clock | Input | Clock | 250 MHz input clock from FPGA PLL |
HPS GMII Interface | |||
mac_tx_clk_o | Input | Conduit | GMII transmit clock from HPS |
mac_tx_clk_i | Output | Conduit | GMII transmit clock to HPS |
mac_rx_clk | Output | Conduit | GMII receive clock to HPS |
mac_rst_tx_n | Input | Conduit | GMII transmit reset source from HPS. Active low reset |
mac_rst_rx_n | Input | Conduit | GMII receive reset source from HPS. Active low reset |
mac_txd[7:0] | Input | Conduit | GMII transmit data from HPS |
mac_txen | Input | Conduit | GMII transmit enable from HPS |
mac_txer | Input | Conduit | GMII transmit error from HPS |
mac_rxdv | Output | Conduit | GMII receive data valid to HPS |
mac_rxer | Output | Conduit | GMII receive data error to HPS |
mac_rxd[7:0] | Output | Conduit | GMII receive data to HPS |
mac_col | Output | Conduit | GMII collision detect to HPS |
mac_crs | Output | Conduit | GMII carrier sense to HPS |
mac_speed[2:0] | Input | Conduit | MAC speed indication from HPS 3'b011: 1G 3'b100: 100M 3'b111: 10M |
PHY RGMII Interface | |||
rgmii_tx_clk | Output | Conduit | RGMII transmit clock to PHY |
rgmii_rx_clk | Input | Conduit | RGMII receive clock from PHY |
rgmii_txd[3:0] | Output | Conduit | RGMII transmit data to PHY |
rgmii_tx_ctl | Output | Conduit | RGMII transmit control to PHY |
rgmii_rxd[3:0] | Input | Conduit | RGMII receive data from PHY |
rgmii_rx_ctl | Input | Conduit | RGMII receive control from PHY |
Clocks
All transmit sequential logic in the HPS GMII to RGMII Adapter Intel FPGA IP is clocked by the HPS PLL for 1000 Mbps speed mode, or by the FPGA PLL during 10/100 Mbps speed mode as shown in the figure below.
All receive sequential logic in the HPS GMII to RGMII Adapter Intel FPGA IP is clocked and driven by external PHY rgmii_rx_clk.