Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.2.4. DMA Controller System Integration

The following figure shows a block diagram of the DMAC and how it integrates into the rest of the HPS system.
Figure 90. DMA Controller Block Diagram

The l4_main_clk clock drives the DMA controller, controller logic, and all the interfaces. The DMA interface uses the AHB protocol and connects directly to the PSS NoC in a peer-to-peer connection. The common registers and channel registers are all accessible as address-mapped registers through this interface.The AHB port supports only SINGLE transfers (hburst =3’b000). The system manager programs a firewall for the target interface.

When the firewall is set for secure operations, only secure transactions are granted access to registers in the controller. Non-secure transactions are blocked and return an error.

When the firewall is not set for secure operations, all transactions secure or non-secure are granted access to registers in the controller.

When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset until software releases it.

For details about reset registers, see section: Reset Signals and Registers in the Reset Manager chapter.