Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.3.7.3. Allocating the Command Queue

  • Allocate memory for the Command queue.
  • Program the SMMU_IDR1.CMDQS to maximum number of Command Queue entries.
  • Set the command base address by writing SMMU_CMDQ_BASE.ADDR register; write the SMMU_CMDQ_BASE.LOG2SIZE as queue size as log2(entries); LOGSIZE must be less than or equal to CMDQS. The Command queue related registers are given.
  • Set the queue read index in SMMU_CMDQ_CONS.RD and queue write index in SMMU_CMDQ_PROD.WR to 0.
Table 100.  Command Queue Related Registers

Register Name

Address

Description

SMMU_CMDQ_BASE_LO_ADDR

0x90

Non-secure Command

Queue Base Address Low

SMMU_CMDQ_BASE_HI_ADDR

0x94

Non-secure Command

Queue Base Address High

SMMU_S_CMDQ_BASE_LO_ADDR

0x8090

Secure Command Queue Base Address Low

SMMU_S_CMDQ_BASE_HI_ADDR

0x8094

Secure Command Queue Base Address High

SMMU_CMDQ_PROD_ADDR

0x98

Non-secure Command

Queue Producer Address

SMMU_S_CMDQ_PROD_ADDR

0x8098

Secure Command Queue Producer Address

SMMU_CMDQ_CONS_ADDR

0x9C

Non-secure Command

Queue Consumer Address

SMMU_S_CMDQ_CONS_ADDR

0x809C

Secure Command Queue Consumer Address

Commands are submitted to SMMU by writing them to the command queue then after ensuring their visibility to SMMU, updating the SMMU_(S)_CMDQ_PROD.WR index which notifies the SMMU there are commands to process.

The actual commands are processed as part of Queue Table Walk (QTW) over ACE-Lite+DVM interface.