Visible to Intel only — GUID: irz1677605540582
Ixiasoft
Visible to Intel only — GUID: irz1677605540582
Ixiasoft
4.1.6. CCU Programming Model
The CCU components and their bases addresses are presented in the HPS Register Map.
After power up, by default, all initiators can access CCU registers and the OCRAM without initializing the CCU. This enables the SDM to download the HPS first stage boot loader (FSBL) to OCRAM and bring the boot core out of reset.
The HPS FSBL contains code to initialize the CCU before any other target is accessible. Each CCU module has a set of registers that is programmed by the HPS FSBL to enable access to other targets.
All CCU registers return to their default value after any POR, cold, watchdog or warm reset. Debug and individual CPU warm resets do not impact the state of the CSRs.