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Ixiasoft
Visible to Intel only — GUID: awl1719871711407
Ixiasoft
13.4.4.9. Bandwidth and Saturation
This section describes encoding bandwidth and saturation values.
Encoding Bandwidth Values
The QoS bandwidth setting is frequency-dependent. Low-frequency initiators require a larger value to achieve the same bandwidth as higher frequency initiators.
You can calculate the register value for a bandwidth as follows:
*I_main_QosGenerator_Bandwidth = ( bandwidth / frequency ) * 256
where bandwidth is in MBps and frequency is in MHz.
For example, to configure the FPGA-to-SDRAM QoS generator for a bandwidth of 1000 MBps at 200 MHz, calculate the register value as follows:
tbu2noc_I_main_QosGenerator_Bandwidth = ( 1000 / 200 ) * 256 = 1280
Encoding Saturation Values
The QoS saturation represents the period of time that the initiator bandwidth is evaluated. The saturation value represents units of 16 bytes of data transferred. For example, a 64-bit initiator that should have the bandwidth re-evaluated every 100 clock cycles would use a saturation setting of 100 cycles * 8 bytes / 16 bytes = 50.
The saturation register controls the number of bytes that the initiator can transmit at full speed before the limiter or regulator takes effect. The register encodes the byte count as a multiple of 16 bytes. Therefore you can calculate the register value as follows:
*I_main_QosGenerator_Saturation = nbytes / 16
For example, to let the MPU initiator send 64 bytes at full speed, calculate the register value as follows:
ccu_dmi0_I_main_QosGenerator_Saturation = 64 / 16 = 4 ccu_dmi1_I_main_QosGenerator_Saturation = 64 / 16 = 4