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Ixiasoft
12.2.2. MPFE and MPFE-lite Differences Among Intel SoC Families
SDRAM Controller Subsystem Features |
Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC |
Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC |
---|---|---|---|---|---|
HPS SDRAM bandwidth |
8, 16, or 32 bits, up to 400 MHz |
16, 32, or 64 bits, up to 1200 MHz |
16, 32, or 64 bits, up to 1066 MHz |
F/I-series: 16, 32, or 64-bits, up to 1600 MHz M-series: 16 or 32 bits, up to 2800 MHz |
16 or 32 bits See Agilex™ 5 FPGAs and SoCs Device Data Sheet for device speed grades. |
Supported SDRAM standards |
DDR3 DDR2 LPDDR2 |
DDR4 DDR3 |
DDR4 DDR3 |
F/I-series: DDR4 (x64/72) M-series: DDR4 (x32+ECC) DDR5 (x32+ECC) LPDDR5 (1x32, 2x16) |
D-series: DDR4 (x32+ECC) DDR5 (x32+ECC) LPDDR4 (1x32, 2x16) LPDDR5 (1x32, 2x16) E-series: Group A: DDR4 (x32+ECC) DDR5 (x32+ECC) LPDDR4 (1x32, 2x16) LPDDR5 (1x32, 2x16) Group B: DDR4 (x32+ECC) LPDDR4 (1x32, 2x16) LPDDR5 (1x32, 2x16) |
FPGA-to-HPS |
32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
128 bits |
Single Port: F/I-series 128, 256, 512 bits Single Port: M-series 128, 256 bits |
256 bits |
FPGA-to-SDRAM available port sizes |
32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
64 bits 128 bits 256 bits |
|
FPGA-to-SDRAM maximum total interface width |
256 bits |
256 bits |
3 x 128 bits = 384 bits total |
512 bits |
256 bits |
Controller implementation |
Dedicated controller in the HPS |
Uses the HMC in the FPGA I/O column, bank 2K |
Uses the HMC in the FPGA I/O column, bank 2L, 2M, 2N |
Uses the HMC in the FPGA I/O column, bank 3C, 3D |
Uses the HMC in the FPGA I/O column, bank 3A, 3B |
External SDRAM interface I/O pin locations |
Fixed locations in the HPS I/O |
Uses DDR I/O in the FPGA I/O column |
Uses DDR I/O in the FPGA I/O column |
Uses DDR I/O in the FPGA I/O column |
Uses DDR I/O in the FPGA I/O column |
Shared access management |
MPFE in the HPS SDRAM controller subsystem |
Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect |
Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect |
Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect |
Arteris FlexNoC scheduler in the HPS MPFE NOC (Version 4.x) |
Device and package support for x64/72 external SDRAM interfaces (64 data bits, 8 ECC bits) |
N/A |
KF40 package only |
All device and package combinations |
All device and package combinations |
See above for supported SDRAM interfaces. |
Supports HPS and core EMIF instances in the same I/O column |
N/A |
No |
Yes |
Yes |
Yes |