Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.6.6.1. Programming Controller in Host Mode

For the following operations, you must program the software to initialize the xHCI using MSI-X as an interrupt mechanism:
  • Initialize the system IO memory maps
  • After Chip reset, wait until the Controller Not Ready (CNR) flag of USBSTS is ‘0’ before writing to any operational registers
  • Program the MAX Device Slots Enabled (MaxSlotsEn) fields in the CONFIG register to enable the device slots that system software is going to use
  • Program the Device Context Base Address Array Pointer (DCBAAP) register with a 64-bit address pointing to where the Device Context Base Address Array is located
  • Define the Command Ring Dequeue Pointer by programming the Command Ring Control register with 64-bit address pointing to the starting address of the first TRB of the Command Ring.
  • Initialize the MSI-X Message Table
    • Initialize Message Control register of the MSI-X Capability Structure
    • Initialize the each active interrupt by:
      • Defining the Event Ring
        • Allocate and initialize the Event Ring Segments
        • Allocate and initialize the Event Ring Segment Table (ERST)
        • Program the Interrupt Event Ring Segment Table Size (ERSTSZ) register with the number of segments provided in Event Ring Segment Table
        • Program the Interrupter Event Ring Dequeue Pointer (ERDP) register with starting address of the first segment described in Event Ring Segment Table
        • Program the Interrupt Event Ring Segment Table Base Address (ERSTBA) with a 64-bit address pointer to where the Event Ring Segment Table is located
        • Define the interrupts
    • Write USBCMD to run the host controller ON via setting the Run/Stop (R/S) bit to ‘1’. This operation allows the xHC to begin accepting doorbell references.

After completing the configuration and the host controller is up and running, then the Root Hub ports start reporting device connects, and so on, and system software begins enumerating devices.

The USB2 (LS/FS/HS) device requires the port reset process to advance the port to the “Enable” state. Once USB2 ports are “Enabled”, the port is active with SOFs occurring on the port, but Pipe Schedule has not yet been enabled. PIPE interface automatically advances to the “Enabled” state if a successful device attach is detected.