Visible to Intel only — GUID: yhm1684439387685
Ixiasoft
Visible to Intel only — GUID: yhm1684439387685
Ixiasoft
5.3.6.5.2. Sector Sizes
The NAND Flash controller supports configurable sector sizes, and the host may choose to program any sector size between the BCH nominal sector size and the maximum sector size allowed by the BCH module (40 bytes). The sector size value to configure does not include the number of ECC checksum bytes. Only even bytes numbers are allowed. The BCH engine adds the ECC checksum to each sector. This checksum is always aligned to 16-bit which is needed for data integrity working in the different operations modes (SDR/DDR).
The alignment should be taken into account when calculating the amount of data written in the page device (user data + metadata + CRC + ECC checksum + padding data). The following table shows the rules that should be followed.
Condition | Amount of Data Alignment |
---|---|
8-bit SDR, param_extended_X_mode = 1 | 8 bits |
8-bit SDR, param_extended_X_mode = 0 | 16 bits |
16-bit SDR, param_extended_X_mode = 1 | 16 bits |
16-bit SDR, param_extended_X_mode = 0 | 32 bits |
NV-DDR/ Toggle mode | 16 bits |
The following fields/registers support the ECC sector configuration:
- sector_size field in the transfer_cfg_1 (0x0404) register. In a page with "n" sectors, this specifies the sector size of the first (n-1) sectors in bytes.
- last_sector_size field in the transfer_cfg_1 (0x0404) register. In a page with "n" sectors, this specifies the sector size of the n-th sector in bytes.
- sector_cnt field in the transfer_cfg_0 (0x0400) register. This register programs the number of sectors to be transferred within a single page.