Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.6.3.4. Receive Descriptor

The DMA in the EMAC attempts to read a descriptor only if the tail pointer is different from the base pointer or current pointer. It is recommended to have a descriptor ring with a length that can accommodate at least two complete packets received by the MAC. Otherwise, the performance of the DMA is impacted greatly because of the unavailability of the descriptors. In such situations, the RX FIFO in MTL becomes full and starts dropping packets.

There are two receive descriptor types: normal and context descriptors. All RX descriptors are prepared by the software and given to the DMA as normal descriptors with the content. The DMA reads this descriptor and after transferring a received packet (or part of packet) to the buffers indicated by the descriptor, the RX DMA closes the descriptor with the corresponding packet status. The format of this status is given in the Receive Normal Descriptor (Write-Back Format) section.

For some packets, the normal descriptor bits are not enough to write the complete status. For such packets, the RX DMA writes the extended status to the next descriptor (without processing or using the buffers pointers embedded in that descriptor). The format and content of this descriptor write back is described in Receive Context Descriptor (Write-Back Format) section.

Receive Normal Descriptor (Read Format)

The format of the receive normal descriptor (read format) is shown in the following figure.
Figure 61. Receive Normal Descriptor (Read Format)
Note: In the receive descriptor (read format), if the buffer address field is all zeros, the EMAC does not transfer data to that buffer and skips to the next buffer or next descriptor.
The following tables describe the RDES0-3 fields for the receive normal descriptor (read format).
Table 131.  RDES0 Normal Descriptor (Read Format)
Bit Name Description
31:0 BUF1AP

Header or buffer 1 address pointer.

When the SPH bit of control register of a channel is reset, these bits indicate the physical address of buffer 1. When the SPH bit is set, these bits indicate the physical address of header buffer where the RX DMA writes the L2/L3/L4 header bytes of the received packet.

The software can program a byte-aligned address for this buffer which means that the LS bits of this field can be non-zero. However, while transferring the start of packet, the DMA performs a write operation with RDES0[3:0] (or RDES0[2:0] in case of 64-bit configuration) as zero. However, the packet data is shifted as per actual offset as given by buffer address pointer.

If the address pointer points to a buffer where the middle or last part of the packet is stored, the DMA ignores the offset address and writes to the full location as indicated by the data-width.

Table 132.  RDES1 Normal Descriptor (Read Format)
Bit Name Description
31:0 BUF1AP

In 64-bit addressing mode, this field contains the most-significant 32 bits of the header/buffer 1 address pointer. Otherwise, this field is reserved.

Table 133.  RDES2 Normal Descriptor (Read Format)
Bit Name Description
31:0 BUF2AP

Buffer 2 address pointer.

These bits indicate the physical address of buffer 2.

When the SPH bit of the DMA_CH(#i)_Control register is set, the buffer address pointer must be bus width-aligned, that is, RDES2[2:0] = 0 corresponding to 64 bus width. LSBs are ignored internally.

When the SPH bit of the DMA_CH(#i)_Control register is reset, the BUF2AP can be of any byte-aligned value. However, the RX DMA uses the LS Bits of the pointer address only while transferring the start bytes of a packet. If the BUF2AP is giving the address of a buffer in which the middle or last part of a packet is stored, the DMA ignores BUF2AP[2:0] (corresponding to 64-bit databus) and writes to the complete location.

Table 134.  RDES3 Normal Descriptor (Read Format)
Bit Name Description
31 OWN

Own bit.

When this bit is set, it indicates that the EMAC DMA owns the descriptor. When this bit is reset, it indicates that the application owns the descriptor.

30 IOC

Interrupt on completion.

When this bit is set, an interrupt is issued to the application when the DMA closes this descriptor.

29:0 BUF2AP Higher 30-bits of the buffer2 address pointer in 64-bit addressing mode. Otherwise it is reserved.

Receive Normal Descriptor (Write-Back Format)

The RX DMA frees up a descriptor by writing it back to the system memory after transferring the received packet contents to the buffers pointed by the descriptor (read format). At the same time, it also writes the status information of the current packet in the format as shown in figure below.
Figure 62. Receive Normal Descriptor (Write-Back Format)
The following tables describe the RDES0-3 fields for the receive normal descriptor (write-back format).
Table 135.  RDES0 Normal Descriptor (Write-Back Format)
Bit Name Description
For Non Tunneled Frames (TNP = 0)
31:16 IVT/ELRD Inner VLAN tag

This field contains the inner VLAN tag of the received packet. This is valid only when double VLAN tag processing and VLAN tag stripping are enabled.

This field is valid only when the L2T field of RDES0 indicates that the received packet is a double VLAN tagged packet.
Note: In case of external receive of inner VLAN lookup, this field shows the lookup index based on the RIVTBS field of the MAC_RVLAN_LKP_SIZE register programming.

External Lookup Result Data

When you enable external lookup function, this field contains the data accepted from the External Lookup Engine (xgmac_elrd_i input) when the ELD=1 and IOS=1. When status bit ELD=0, then this field corresponds to IVT.

15:0 OVT/ELRD Outer VLAN tag

This field contains the outer VLAN tag of the received packet. This is valid only when VLAN tag stripping is enabled.

This field is valid only when the L2T field of RDES0 indicates that the received packet is a VLAN or doubled VLAN tagged packet.
Note: In case of external receive of outer VLAN lookup, this field shows the lookup index based on the ROVTBS field of the MAC_RVLAN_LKP_SIZE register programming.

External lookup result data

When you enable external lookup function, this field contains the data accepted from the external lookup engine (xgmac_elrd_i input) when the ELD=1 and IOS=0. When status bit ELD=0, then this field corresponds to OVT.

For Tunneled Frames (TNP = 1)
31:8

VNID/VSID

VNID/VSID tag.

This field contains VNID for VxLAN type tunneled packet and VSID for NVGRE type tunneled packets.

7:3 RSVD Reserved
2:0 OL2L3

Outer L2 L3 type.

This field indicates the type of outer header of the received tunneled packet.
  • 001: untagged IPv6
  • 010: VLAN tagged IPv4
  • 011: VLAN tagged IPv6
  • 100: Double VLAN tagged IPv4
  • 101: Double VLAN tagged IPv6
  • 110-11: Reserved
Table 136.  RDES1 Normal Descriptor (Write-Back Format)
Bit Name Description
31:0

RSSH/FRPLI

Received side scaling hash/FRP last instruction.

When RDES3[26] bit is set and RSS hash feature is enabled, this field contains the 32-bit RSS hash calculated with some of the L3-L4 header fields of the current packet.

For a tunneled packet, this contains the non-standard RSS hash using some of the outer header and inner header fields.
Note: In case of an external RSS lookup, based on RSS lookup size, LSB of this field can be used to determine the lookup index.

When RDES3[26] bit is reset and FRP feature is enabled, this field contains the FRP last instruction number where FRP result is generated.

In case of non-receive channel list based frame duplication, when the packet is duplicated to multiple receive DMA channels, EMAC does not provide the RSS hash.

Table 137.  RDES2 Normal Descriptor (Write-Back Format)
Bit Name Description
31:29 L3L4FM

Layer 3 and Layer 4 filter number matched.

When the DHLFRS field of the MAC_Packet_Filter register is set to
  • 0x1: This field represents DA hash table index [10:8] bits, if it is valid, based on HFDAF field.
  • 0x2: This field is reserved. If bit 28 or bit 27 is set to 1, the MADRM field of the same status word indicates the layer 3 and layer 4 filter number that matched the received packet.
For all other cases, these bits indicate the number of the layer 3 and layer 4 filter that matched the received packet:
  • 000: Filter 0
  • 001: Filter 1
  • 010: Filter 2
  • 011: Filter 3
  • 100: Filter 4
  • 101: Filter 5
  • 110: Filter 6
  • 111: Filter 7

This field is valid only when bit 28 or bit 27 is set to 1. When more than one filter matches, these bits give the lowest filter number.

When more than one filter matches, these bits indicate the number of the lowest filter. For a tunneled packet, only the outer L3-L4 header fields are used for comparison.

28 L4FM

Layer 4 Filter Match.

When this bit is set, it indicates that the received packet matches one of the enabled Layer 4 Port Number fields. This status is given only when one of the following conditions is true:

  • Layer 3 fields are not enabled and all enabled layer 4 fields match
  • All enabled Layer 3 and layer 4 filter fields match

When more than one filter matches, this bit gives the layer 4 filter status of filter indicated by the following bits of the status word.

  • MADRM[5:0]: When DHLFRS field of MAC_Packet_Filter register is set to 0x02
  • Bits[31:29]: Otherwise

For a tunneled packet, only the outer L3-L4 header fields are used for filter comparison.

27 L3FM

Layer 3 filter match.

When this bit is set, it indicates that the received packet matches one of the enabled layer 3 IP address fields. This status is given only when one of the following conditions is true:
  • All enabled layer 3 fields match and all enabled layer 4 fields are bypassed
  • All enabled filter fields match
When more than one filter matches, this bit gives the layer 3 filter status of filter indicated by the following fields of the status word:
  • MADRM[5:0]: When DHLFRS field of MAC_Packet_Filter register is set to 0x02
  • Bits[31:29]: Otherwise

For a tunneled packet, only the outer L3-L4 header fields are used for filter comparison.

26:19 MADRM

MAC Address Match or Hash Value or L3L4 Filter Match.

  • When the DHLFRS field of the MAC_Packet_Filter register is set to 0x0 or 0x1:
    • When (DAIF = 0 and HFDAF = 2'b00) or (DAIF = 1 and HFDAF = 2'b01), this field contains the MAC address register number that matched the destination address of the received packet.
    • When (DAIF = x and HFDAF = 2'b1x), this field contains the hash value computed by the MAC. A packet passes the hash filter when the bit corresponding to the hash value is set in the hash filter register.

For other combinations of DAIF and HFDAF, this field is unused.

  • When the DHLFRS field of the MAC_Packet_Filter register is set to 0x2:
    • If Bit 28 or Bit 27 is set to 1, MADRM field indicates the Layer 3 and Layer 4 filter number that matched for the received packet. The number of lower bits of the MADRM (1, 2, 3, 4, or 5 bits) that are valid is based on the number of L3-L4 filters selected (2, 4, 8, 16, or 32); remaining bits are reserved.
  • When the DHLFRS field of the MAC_Packet_Filter register is set to 0x3:
    • This field is reserved.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.

18:17 HFDAF

Hash Filter and Destination Address Filter Status.

This field gives combined result for both Hash DA and Perfect DA filter status.

  • When DAIF = 0
    • 2’b00: Perfect DA filter pass and don't care Hash DA filter.
      • When DHLFRS is 0x0 or 0x1. MADRM = MAC address register number that matched the DA of the received packet.
    • 2’b01: Both Perfect DA filter and Hash filter fail
      • When DHLFRS is 0x0 or 0x1, MADRM = unused.
    • 2’b1x: Perfect DA filter fail and Hash filter pass
      • When DHLFRS = 0,
        • x = 0 and MADRM = [7:0] bit of DA hash table index.
      • When DHLFRS = 1,
        • x = 11th bit, if DA hash table size>2048
        • x = 0, otherwise.
        • L3L4M = [10:8] bit and MADRM = [7:0] bit of DA hash table index
      • When DHLFRS != (0 or 1)
        • x = 0
  • When DAIF = 1
    • 2’b00: Perfect DA filter pass (no match for Perfect DA) and Hash DA filter pass (no match for Hash DA)
      • When DHLFRS is 0x0 or 0x1, MADRM = unused
    • 2’b01: Perfect DA filter fail (match for Perfect DA) and don't care Hash DA filter
      • When DHLFRS is 0x0 or 0x1, MADRM = MAC address register number that matched the DA of the received packet
    • 2’b1x: Perfect DA filter pass (no match for Perfect DA) and Hash DA filter fail (match for Hash DA).
      • When DHLFRS = 0
        • x = 1 and MADRM = [7:0] bit of DA hash table index
      • When DHLFRS = 1
        • x = 11th bit, if DA hash table size > 2048
        • x = 0, otherwise.
        • L3L4M = [10:8] bit and MADRM = [7:0] bit of DA hash table index
      • When DHLFRS != (0 or 1)
        • x = 1

For a tunneled packet, only the outer Ethernet header fields are used for filtering

17 DAF

Destination Address Filter Fail.

When this bit is set, it indicates that the packet failed the DA Filter in the MAC.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.

16 SAF

SA Address Filter Fail.

When this bit is set, it indicates that the packet failed the SA Filter in the MAC.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.

15 VF

VLAN Filter Status.

When this bit is set, it indicates that the VLAN Tag of received packet passed or bypassed the VLAN filter.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.

14 RPNG

Response Packet Not Generated.

For ARP packets, this bit is set when the MAC is busy transmitting ARP reply to earlier ARP request (only one ARP request is processed at a time or when the Register bit ARPEN = 0).

Similarly, for PTP packets, this bit is set when the MAC is busy transmitting a PTP response to an earlier PTP packet.

This bit is reserved when the Enable IPv4 ARP Offload option or PTP Offload feature are not selected.

RPNG field is reserved for tunneled packet.

13 IOS

IVT-OVT Select.

This bit when set to 1 and when ELD=1, indicates that RDES0[31:6] field is interpreted as ELRD and contains the data read from the External Lookup Interface (xgmac_elrd_i bus).

When this bit is 0 and ELD=1, then RDES[15:0] contains the ELRD field.

This bit is reserved when “Enable External Lookup Interface” is not selected or when current packet is a tunneled packet (TNP=1).

12 ELD

ELRD valid.

This bit, when set to 1 indicates that either RDES0[31:6] field or RDES[15:0] field is interpreted as ELRD and contains the data read from the External Lookup Interface (xgmac_elrd_i bus). When this bit is 0, RDES0 reverts back to the default IVT, OVT fields. This bit is valid and set only when ELEN is set in MAC_Rx_Configuration register and the xgmac_elrd_val_i input signal from the External Lookup interface is active for this packet.

This bit is reserved when “Enable External Lookup Interface” is not selected or when current packet is a tunneled packet (TNP=1).

11 TNP

Tunnel Packet.

When this field is ‘1’, received packet is a tunneled packet. When this field is ‘0’, received packet is a non-tunneled packet. Tunneled packet recognition is enabled only when VNE of MAC_Tx_Configuration register is set.

Note: This field exists only when the EDMA field of the MAC_HW_Feature0 register is selected; Otherwise this field is Reserved.

10 RSVD Reserved
9:2 HL

L3/L4 Header Length.

This field contains the length of the header of the packet split by the MAC at L3 or L4 header boundary as identified by the MAC receiver. This field is valid only when the first descriptor bit is set (FD = 1).

The header data is written to the Buffer 1 address of corresponding descriptor. If header length is zero, it implies that the MAC did not identify and split the header and both Buffer 1 and Buffer 2 are used for storing the packet.

For VxLAN tunneled packets, header length = (header length of outer packet + eight bytes of VxLAN header + header length of inner packet).

For NVGRE tunneled packets, header length = (outer packet’s header length +inner packet’s header length).

This field is valid when the Enable Split Header Structure option is selected.

1 AVTDP

AV Tagged Data Packet.

When L34T = 0000, this bit is set to 1 when AV Tagged Data packet is received.

When L34T is non-zero, this bit is HL[1] for packet split by the MAC at L3 or L4 header.

0 AVTCP

AV Tagged Control Packet.

When L34T = 0000, this bit is set to 1 when AV Tagged Control packet is received.

When L34T is non-zero, this bit is HL[0] for packet split by the MAC at L3 or L4 header.

In the write-back format, all the status fields (except bits[31:28]) are valid only for the last descriptor (when RDES3[28] is set).

Table 138.  RDES3 Normal Descriptor (Write-Back Format)
Bit Name Description
31 OWN

Own Bit.

DMA clears this bit (to 0) to indicate that it has transferred the data to the buffers and the descriptor is now owned by the software. The DMA clears this bit when either of the following conditions is true:

  • The DMA completes the packet transfer
  • The buffers associated with the descriptor are full
30 CTXT

Receive Context Descriptor.

When this bit is set, it indicates that the current descriptor is a context type descriptor. The DMA writes 1'b0 to this bit for normal receive descriptor.

29 FD

First Descriptor.

1: Indicates that this descriptor contains the first buffer of the packet.

If the size of the first buffer is 0, the second buffer contains the beginning of the packet. If the size of the second buffer is also 0, the next descriptor contains the beginning of the packet.

CTXT, FD, and LD bits together indicate Descriptor Definition Error. During write-back, all three bits are set to 1 {CTXT, FD, LD} = 3’b111, to indicate Descriptor Definition Error in the Rx Descriptor. Descriptor Definition Error for Rx Descriptor is indicated when both Buffer-1 and Buffer-2 are all 1s. On encountering this error, the Receive DMA terminates the ongoing DMA transfer, flushes the ongoing packet in the Receive Queue and enters stop state.

The DEE and RPS fields of the corresponding DMA_CH(#i)_Status register is set to 1.

Recovery Mechanism: Perform a software reset by programming the SWR field of the DMA_Mode register to 1.

28 LD

Last Descriptor.

When this bit is 1,

  • Indicates that the buffers to which this descriptor is pointing. Contains end of packet.
  • Rest of the status fields in RDES0, RDES1, and RDES3 provide information about the packet.
27 CDA

Context Descriptor Available.

When this bit is set, the next descriptor following this descriptor is a Context Descriptor.

26 RSV

RSS Valid.

When this bit is set, it indicates that valid RSS Hash is available in RDES1[31:0]. This bit is valid only when the RSS function is enabled MAC_RSS_Control register. In case of non-receive channel list based frame duplication, when packet is duplicated to multiple Receive DMA channels, this field is 0.

25 ISP

In Sequence Packet.

When this bit is reset, it indicates that this packet is not in sequence (TCP sequence number) with respect to the previous packet transferred by this DMA, or the RSS Hash value is different for this packet with respect to the RSS Hash calculated and given for the previous packet.

When this bit is set, it indicates that this TCP packet is in sequence with respect to the previous packet transferred by this DMA and the RSS hash values also match. The application can do a TCP coalescing of this packet with the previous packet transferred by this DMA.

This bit is valid only when the OoS function is enabled in MAC_RSS_Control register. This bit is not valid if it is a tunneled packet.(TNP=1)

24

ETM/

NCP

Ether Type Match / No Coalescing Packet.

When L34T=000, this bit is set to 1 (ETM Status) when the “Type” field of the received packet matches the value programmed in the MAC_Rx_Eth_Type_Match register.

When L34T has any value other than 000 and this bit is set to 1 (NCP Status), it indicates that the DMA has received a packet that must not be kept holding for TCP packet coalescing. It must be forwarded to the TCP/IP stack immediately even though it may be in sequence with respect to the previous packet.

NCP Status is valid only when the OoS function is enabled in the MAC_RSS_Control register.

For a tunneled packet, ETM refers to the Type Match of the Inner Ethernet Header.

NCP is not supported for a tunneled packet.

23:20 L34T

Layer3 / Layer4 packet Type.

These bits indicate the type of payload encapsulated in the IP datagram and processed by the Receive Checksum Offload Engine (RxCOE).

For a tunneled packet, the Layer3/Layer4 packet type refers to the L3/L4 type of the inner packet.

This field is valid only when the LD field is set.

  • 0000: Not an IP packet
  • 0001: IPv4 packet with TCP Payload as Layer4
  • 0010: IPv4 packet with UDP Payload as Layer4
  • 0011: IPv4 packet with ICMP Payload as Layer4
  • 0100: IPv4 packet with IGMP Payload is Layer4
  • 0101 to 0110: Reserved
  • 0111: IPv4 with unknown (unsupported) payload
  • 1000: Reserved
  • 1001: IPv6 packet with TCP Payload as Layer4
  • 1010: IPv6 packet with UDP Payload as Layer4
  • 1011: IPv6 packet with ICMP Payload as Layer4
  • 1100 to 1110: Reserved
  • 1111: IPv6 with unknown (unsupported) payload
19:16 ET/LT

Error Type or L2 Type.

When the 15th bit of this descriptor (ES) is set to 1, this field indicates the Error Type.

When the 15th bit of this descriptor (ES) is set to 0, this field indicates the L2 Packet Type.

Following is the encoding:

When ES = 1 (Error Type Encoding)

  • 0000: Reserved
  • 0001: Watchdog Timeout Error
    • It indicates that the Receive Watchdog Timer has expired while receiving the current packet.
    • The current packet is truncated after watchdog timeout.
  • 0010: Invalid Code Error or GMII Error
    • In GMII mode, it indicates that the RX_ER and RX_DV signals were asserted for the frame, indicating a receive error signaled to the GMII.
  • 0011: CRC Error
    • It indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received packet.
  • 0100: Giant Packet Error
    • It indicates that the packet length exceeds the specified maximum Ethernet size of 1518,1522, or 2000 bytes (9018 or 9022 bytes if jumbo packet enable is set).
    • Note: Giant packet indicates only the packet length. It does not cause any packet truncation.
  • 0101: IP Header Error
    • It indicates that the 16-bit IPv4 Header checksum calculated by the EMAC controller does not match the received Checksum bytes or that the IP datagram version is not consistent with the Ethernet Type value.
    • This error is possible only when you select the Enable Receive TCP/IP Checksum Check feature
  • 0110: Payload (L4) Checksum Error
    • It indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) calculated by the EMAC controller does not match the received TCP, UDP, or ICMP checksum field.
  • 0111: Overflow Error
    • It indicates that the received packet is damaged because of buffer overflow in Rx FIFO.
    • Note: This bit is set only when the DMA transfers a partial packet to the application. This happens only when the Rx FIFO is operating in the threshold mode. In the store-and-forward mode, all partial packets are dropped completely in Rx FIFO.
  • 1000: Bus Error
    • It indicates that Bus Error response is received while fetching this descriptor or when packet is being transferred to its buffers.
  • 1001: Length Error
    • It indicates that the Length value of the current frame is inconsistent with the total number of bytes received in the current frame. This is applicable when Frame Length value is less than 1500. This error is reported when the following type of frames are received:
    • Frames in which the value of the Length field is less than 46 bytes and the length of the received frame is less than the following:
    • Length field + 18 bytes
    • Frames in which the value of the Length field is equal to or greater than 46 bytes and the length of the received frame is not equal to the following:
    • Length field + 18 bytes
  • 1010: Good runt packet. Packet less than 64 bytes but with good CRC.
  • 1011: Reserved
  • 1100: Dribble Error
    • Indicates that, in the 10/100Mbps speed mode, the packet has ended without a byte boundary.
  • 1101 -1110: Reserved for non-tunneled packets
  • 1111: Safety Error
    • In the case of tunneled packet (TNP = 1), the error status is extended to differentiate between the errors in outer Header or Inner Header. In the status types, the following values are applicable for the Outer Header fields:
  • 0101: Outer IP Header Error
  • 0110: Outer Header's Payload (L4) Checksum Error
    • Additionally, the following Error Status types are applicable
  • 1001: Inner Packet IP Header Error
  • 1010: Inner Packet Payload (L4) Checksum Error
  • 1101-1110: Reserved for tunneled packets
    • When ES = 0 (L2 Packet Type Encoding)
  • 0000: The packet is a length packet.
  • 0001: The packet is a MAC Control packet.
  • 0010: DCB Control Packet.(Note: Inner Header of a tunneled packet is not parsed for DCB Control type)
  • 0011: The packet is of ARP Request Packet Type.
  • 0100: The packet is of OAM packet type.(Note: Inner header of a tunneled packet is not parsed for OAM Control type)
  • 0101: The untagged packet has a Type field which matched the value in the MAC_Rx-_Eth_Type_Match register
  • 0110 – Untagged AV Control packet
  • 0111: The packet is an other Type Packet.
  • 1000: The packet is type packet with Single SVLAN tag.
  • 1001: The packet is type packet with Single CVLAN tag.
  • 1010: The packet is type packet with Double VLAN tag with outer VLAN is CVLAN and inner is also CVLAN.
  • 1011: The packet is type packet with Double VLAN tag with outer VLAN is SVLAN and inner is SVLAN.
  • 1100: The packet is type packet with Double VLAN tag with outer VLAN is SVLAN and inner is CVLAN
  • 1101: The packet is type packet with Double VLAN tag with outer VLAN is CVLAN and inner is SVLAN.
  • 1110 - 1111: Reserved

For a tunneled packet, the L2 packet type encoding refers to the L2 type of the Inner packet.

15 ES

Error Summary.

This bit indicates that the received packet has an error. The type of error is indicated by bits

[19:16].

This field is valid only when the LD bit of RDES3 is set.

When this field is 1, indicates safety error.

14 RSVD Reserved
13:0 PL

Packet Length.

These bits indicate the byte length of the received packet that was transferred to system

memory. This does not include the VLAN/Pad/CRC bytes if VLAN/Pad/CRC stripping is

enabled. This field is valid when the LD (bit[28]) field of RDES3 is set and there is no

overflow error indication in ET/LT(bits[19:16]).

Receive Context Descriptor (Write-Back Format)

The receive context descriptor provides information about the extended status of the last received packet. Bit 30 of RDES3 indicates the context type descriptor.
Figure 63. Receive Context Descriptor
Table 139.  RDES0 Context Descriptor
Bit Name Description
31:0 RTSL

Receive packet timestamp low.

The DMA updates this field with the least significant 32 bits of the timestamp captured for the corresponding receive packet. When this field and the RTSH field of RDES1 show a value of all ones, the timestamp must be considered as corrupt.

Table 140.  RDES1 Context Descriptor
Bit Name Description
31:0 RTSH

Receive packet timestamp high.

The DMA updates this field with the most significant 32 bits of the timestamp captured for the corresponding receive packet. When this field and the RTSH field of RDES1 show a value of all ones, the timestamp must be considered as corrupt.

Table 141.  RDES2 Context Descriptor
Bit Name Description
31:0 RSVD

Reserved

Table 142.  RDES3 Context Descriptor
Bit Name Description
31 OWN

Own bit.

DMA clears this bit to 0, to indicate that the status is written in the descriptor and is now owned by the software.

30 CTXT

Receive context descriptor.

When this bit is set, it indicates that the current descriptor is a context descriptor. The DMA writes 1'b1 to this bit for context descriptor.

29:20 RSVD Reserved
19:16 ET/ST

Error type/Status type.

  • When ES = 1, this field indicates the error type
  • When ES = 0, this field indicates status type

Status type

  • 0000 - 1111: Reserved

Error type

  • 0000 - 1110: Reserved
  • 1111: Safety Error
15 ES

Error summary.

  • 1: Indicates that ET/ST (bits 19:16) is error type
  • 0: Indicates that ET/ST (bits 19:16) is status type
14:7 RSVD Reserved
6 TSD

Timestamp dropped.

When set, it indicates that a timestamp was captured for this packet but was dropped due to the lack of space in Rx FIFO. The host must consider the RTSL and RTSH as valid only when TSD=0 and TSA=1

5 PRPNG

PTP response packet not generated.

When set, it indicates that a PTP Response packet was not generated by the MAC for this received PTP Packet. This bit is valid only when the PTP Offload Feature is enabled in your configuration.

4 TSA

Timestamp available.

When set, this bit indicates that the timestamp value is available in RDES0 and RDES1 of the context descriptor.

3:0 PMT

PTP message type:

These bits are encoded to give the type of the PTP message received:

  • 0000: No PTP message received
  • 0001: SYNC (all clock types)
  • 0010: Follow-up (all clock types)
  • 0011: Delay_Req (all clock types)
  • 0100: Delay_Resp (all clock types)
  • 0101: Pdelay_Req (in peer-to-peer transparent clock)
  • 0110: Pdelay_Resp (in peer-to-peer transparent clock)
  • 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
  • 1000: Announce
  • 1001: Management
  • 1010: Signaling
  • 1011-1110: Reserved
  • 1111: PTP packet with Reserved message type