Visible to Intel only — GUID: hfm1678563806072
Ixiasoft
Visible to Intel only — GUID: hfm1678563806072
Ixiasoft
5.7.4.1. USB 2.0 ULPI PHY Signal Description
Signal Name | Width | Direction | Description |
---|---|---|---|
USB_CLK | 1 | Input | ULPI Clock. Receives the 60-MHz clock supplied by the high-speed ULPI PHY. |
USB_DIR | 1 | Input | ULPI Data Bus Control 1 - The PHY has data to transfer to the USB OTG controller. 0 - The PHY does not have data to transfer. |
USB_NXT | 1 | Input | ULPI Next Data Control. Indicates that the PHY has accepted the current byte from the USB OTG controller. When the PHY is transmitting, this signal indicates that a new byte is available for the controller. |
USB_STP | 1 | Output | ULPI Stop Data Control. The controller asserts this signal for one clock cycle to indicate the end of a USB transmit packet or a register write operation and, optionally, to stop packet reception. |
USB_DATA[7:0] | 8 | Bidirectional | Bidirectional data bus. Driven low by the controller during idle. |