Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.5.2. FPGA EMAC I/O Signals

Three Ethernet Media Access Controllers are provided in the HPS. The table below describes the signals that are available from each Ethernet Media Access Controller to the FPGA I/O. The EMAC uses the Gigabit Media Independent Interface (GMII) interface to route the signals through the FPGA fabric.

For more information, refer to supported EMAC PHY interfaces through the FPGA fabric in Interfaces chapter.

Note: In the table below, the asterisk (*) in the signal names indicates the EMAC peripheral number.
Table 113.  FPGA EMAC I/O Signals
Signal Name Signal Type Direction Width Description
emac*_mac_speed[2:0] Speed Out 3 These output signals indicate the EMAC speed mode.
  • 3'b010 = 2.5 Gbps
  • 3'b011 = 1 Gbps
  • 3'b100 = 100 Mbps
  • 3'b111 = 10 Mbps

emac*_mac_tx_clk_i

Transmit Clock In 1

This is the transmit clock (2.5 MHz/25 MHz) provided by the PHY in 10/100 Mbps modes.

This clock is not used in 1/2.5 Gpbs speed mode.
Note: This clock must be able to perform glitch-free switching between 2.5 and 25 MHz. This clock is equivalent to the datapath clock emac_clk_tx_i.
emac*_mac_tx_clk_o Transmit Clock Output Out 1

In 1/2.5 Gpbs speed mode, this signal is the transmit clock output to the PHY to sample data.

For 2.5 Gbps speed mode, the transmit clock frequency is 312.5 Mhz.

For 1 Gbps speed mode, the transmit clock frequency is 125 Mhz.

For 10/100 Mbps speed, this clock is not used by the PHY, however the transmit clock input from the PHY in 10/100 Mbps modes of operation (input on emac_clk_tx_i) is muxed onto this clock output and should be used for the synchronous clock by any adaptation logic on the transmit data and control path in the FPGA fabric for GMII modes.

emac*_mac_txd_o[7:0] PHY Transmit Data Out 8

These are a group of eight transmit data signals driven by the EMAC.

All eight bits provide the GMII transmit data byte. For the lower speed with 10/100 Mbps modes of operation, only bits[3:0] are used. The validity of the data is qualified with phy_txen_o and phy_txer_o. Synchronous to phy_txclk_o.

emac*_mac_txen

PHY Transmit Data Enable

Out 1

This signal is driven by the EMAC. When driven high, this signal indicates that valid data is being transmitted on the phy_txd_o bus.

emac*_mac_txer PHY Transmit Error Out 1 This signal is driven by the EMAC and when high, indicates a transmit error or carrier extension on the phy_txd_o bus. It is also used to signal low power states in energy efficient Ethernet operation.
emac*_mac_rst_tx_n

Transmit Clock Reset output

Out 1

Transmit clock reset output to the FPGA fabric, which is the internal synchronized reset to phy_txclk_o output from the EMAC. It is generated to the clk_tx_i clock during software reset.

May be used by logic implemented in the FPGA fabric as desired. The reset pulse width of the rst_clk_tx_n_o signal is three transmit clock cycles.

emac*_mac_rx_clk

Receive Clock In 1

Receive clock from external PHY.

For 2.5 Gbps speed mode, the receive clock frequency is 312.5 Mhz.

For 1 Gbps speed mode, the receive clock frequency is 125 Mhz.

For 100 Mbps speed mode, the receive clock frequency is 25 Mhz.

For 10 Mbps speed mode, the receive clock frequency is 2.5 Mhz.

Note: This clock is equivalent to the datapath clock emac_clk_rx_i.
emac*_mac_rxd[7:0] PHY Receive Data In 8

This is an eight-bit receive data bus from the PHY. In 1/2.5 Gbps speed mode, all eight bits are sampled. The validity of the data is qualified with phy_rxdv_i and phy_rxer_i. For lower speed 10/100 Mbps speed operation, only bits [3:0] are sampled.

These signals are synchronous to clk_rx_i.

emac*_mac_rxdv PHY Receive Data Valid In 1 This signal is driven by PHY. When driven high, it indicates that the data on the phy_rxd_i bus is valid. It remains asserted continuously from the first recovered byte of the frame through the final recovered byte.
emac*_mac_rxer PHY Receive Error In 1

This signal indicates an error or carrier extension in the received frame.

This signal is synchronous to clk_rx_i.

emac*_mac_rst_rx_n

Receive clock reset

output.

Out 1

Receive clock reset output to the FPGA fabric, generated synchronous to the clk_rx_i during software reset.

The reset pulse width of the rst_clk_rx_n_o signal is three transmit clock cycles.

emac*_mac_crs PHY Carrier Sense In 1 This signal is asserted by the PHY when either the transmit or receive medium is not idle. The PHY de-asserts this signal when both transmit and receive interfaces are idle. This signal is not synchronous to any clock.
emac*_mac_col PHY Collision Detect In 1 This signal, valid only when operating in half duplex, is asserted by the PHY when a collision is detected on the medium. This signal is not synchronous to any clock