Visible to Intel only — GUID: mks1676326112516
Ixiasoft
Visible to Intel only — GUID: mks1676326112516
Ixiasoft
11.5.2. HPS-to-FPGA Bridge
The H2F bridge provides a configurable-width, high-performance master interface to the FPGA fabric. You can configure the bridge master exposed to the FPGA fabric for 32/64/128-bit data from HPS component parameter editor, available in Platform Designer and the IP catalog. The bridge provides most managers in the HPS with access to logic and peripherals implemented in the FPGA. Additional IPs implemented in the FPGA can be used as part of the HPS subsystem.
The H2F bridge sits in between the AXI-4 32/64/128-bit network interface units (NIU) of the PSS NOC and the boundary of the HPS. The bridge contains multiplexing, register slice. On the PSS NOC, 3 dedicated target NIUs of 32/64/128-bit are instantiated. The bridge multiplexes outputs from all 3 NIUs into a single AXI bus before going into the FPGA. The following figure shows the block diagram for the H2F bridge.
The following table lists the ports for the H2F.
Name | Direction | Description |
---|---|---|
hps2fpga_axi_clock | Input | Clock from a single source in the FPGA. |
hps2fpga_axi_reset | Input | Async active high reset to the bridge. |
soc2fpga_port_size_config[2:0] | Input | [2]: reserved. [1:0]: Port width selection:
|
The following table shows the properties of the H2F bridge.
Bridge Property | Value |
---|---|
Protocol | AXI-4 |
Clock | hps2fpga_axi_clock (from FPGA) |
Data Width | 32/64/128 |
Address Width | 38 |
ID Width | 4 |
A*Region Width | 0 |
A*Len Width | 8 |
A*QoS Width | 0 |
FIXED Burst | Yes |
Exclusive Support | Yes (external monitor) |
Min Narrow Burst Size | 1 byte |
Max Wrap Burst Size | 64 bytes52, 128 bytes53 |
nPendingTrans (Issuance/Acceptance) | 16 |
nPendingOrderID | 16 |
Ready latency requirement | Yes |