Visible to Intel only — GUID: qmq1679592395371
Ixiasoft
Visible to Intel only — GUID: qmq1679592395371
Ixiasoft
5.8.7.4.4. Private Read/Write Transfers
The programming flow for I3C private transfers in master mode of I3C controller consists of different phases as shown in the following figure:
The four main phases are explained in this section.
- Issue private transfers
The issue private transfers phase generates the command with the private write/read transfer to the respective slave.
Procedure:
The following settings are done for the command and then written to the controller through COMMAND_QUEUE_PORT register.
The application has to write the following combination of the commands based on their required private transfer, with or without data:
- Transfer command with short data argument packet, if the data length is less than 3 bytes.
- Transfer command with transfer argument, if the data length is more than 3 bytes.
- Read transfer command with transfer argument
The following are the required transfer command settings in the COMMAND_QUEUE_PORT register:
- Set CP bit to 0.
- Ignore CMD field, as it is invalid for the private transfers.
- Point the Device Address Table for the respective slave address with the DEV_INDX field.
- If the targeted device is I2C, then application has to set the DEV_ADDR_TABLEx_LOCx[31] to 1.
- If the targeted device is I3C, then application has to set the DEV_ADDR_TABLEx_LOCx[31] to 0.
- Set RnW bit to either 1 (read) or 0 (write) based on private transfer.
- Push data to transmit FIFO
The push data to transmit FIFO phase continuously fills the data to the transmit FIFO based on the command issued in COMMAND_QUEUE_PORT register.
Procedure
The application pushes the data (in Word) to the Tx-FIFO based on the command issued to the COMMAND_QUEUE_PORT register.
The application can push the data in either of the following ways:
- PIO mode: The CPU can monitor the threshold status signal (INTR_STATUS[TX_THLD_STS]) and then push the data to the Tx-FIFO through TX_DATA_PORT.
- DMA mode: The DMA transfers the data as soon as I3C controller requests the DMA through the DMA signals (dma_tx_req, dma_tx_single).
- Retrieve data from Rx-FIFO
The retrieve data from Rx-FIFO phase continuously retrieves the data from the receive FIFO based on the command issued in COMMAND_QUEUE_PORT register.
Procedure:
The application retrieves the data (in Word) from the Rx-FIFO based on the command issued to the COMMAND_QUEUE_PORT register.
The application can fill the data in either one of the following ways:
- PIO mode: The CPU can monitor the threshold status signal (INTR_STATUS[RX_THLD_STS]) and then pop the data from the Rx-FIFO through RX_DATA_PORT.
- DMA mode: The DMA retrieves the data as soon as I3C controller requests the DMA through DMA signals (dma_rx_req, dma_rx_single).
- Check response status
The check response status phase detects the generation of Response status and reads it to know the status of the issued transfer.
Procedure
The INTR_STATUS[RESP_READY_STS] interrupt indicates the response available status and the application can read the available response through RESPONSE_QUEUE_PORT register.