Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: eaw1675368429556
Ixiasoft
Visible to Intel only — GUID: eaw1675368429556
Ixiasoft
4.3.3.5. APB4 Programming Interface
This interface enables the CPUs to read and write configuration registers in the MMU-600.
Based on the parameter setting, TCUCFG_NUM_TBU as 14, the APB address required for TCU is 21-bit. Although SMMU needs only 21-bit (2MB) address, but 16MB address (24-bit) space is allocated. For software, firmware, and validation, accesses to SMMU should be restricted to only 21-bit (2MB) of address space. Any access over the 2MB is unknown behavior for SMMU.