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4.1.5.4.4. Interleaving
CCU supports interleaving across snoop filters and system caches. This capability enables higher access bandwidth and eases physical design of the chip. Snoop filters are implemented within DCE and can be interleaved/distributed across the two DCE instances. System caches are implemented within DMI.
DMIs can be interleaved/distributed as a memory interleave group (MIG) of 1, 2, or 4 DMIs. Multiple memory interleave groups form a memory interleave group set (MIGS). On Agilex™ 5, there is a single MIG consisting of DMI0 and DMI1. See Address Map When Using Multiple SDRAM Channels.