Visible to Intel only — GUID: spm1679314261614
Ixiasoft
Visible to Intel only — GUID: spm1679314261614
Ixiasoft
5.6.5.11. USB 3.1 Gen1 Controller Clocks
The following figure shows the USB 3.1 controller clocks.
This section describes the USB 3.1 Gen1 controller clocks amd provides the clocks specifications in the following table.
Clock Name | Source | IP Clock Name | Frequency | Description |
---|---|---|---|---|
l4_main_clk | Clock manager | Bus_clk_early | 400 Mhz | AHB/AXI clock. This input is the clock from the application bus. |
ulpi_clk | IO | ulpi_clk | 600 Mhz | ULPI clock from PHY. The negative edge is also used in DDR mode. Select ulpi_clk as a test clock when configuring the core for a ULPI. |
pipe_pclk | PHY Generated | Pipe_pclk | 250 Mhz | This is the pipe output clock from the PHY. It is the capture and logic clock for the PIPE3 inputs to controller. SuperSpeed mode:
This clock is running although a USB 2.0 device is connected. The USB 3.1 controller has dependency to propagate the internal resets with PIPE clock. |
suspend_clk | suspend_clk | 24/200 MHZ | Suspend clock. During boot time, it works with 200 MHz, after that it moves to 20 MHz clock. |
|
ref_clk | ref_clk | 24/200 Mhz | Reference clock. During boot time, it works with 200MHz, after that it moves to 20 MHz clock |
|
ram_clk_in | ram_clk_in | RAM input clock. It is connected through a loopback from ram_clk_out. |
The following figure shows the USB 3.1 controller clock diagram.