Visible to Intel only — GUID: gxn1675816862655
Ixiasoft
Visible to Intel only — GUID: gxn1675816862655
Ixiasoft
5.4.6.3.1. SDMA Operation
The simple (single operation) DMA mode uses SD host registers to describe the data transfer. The SDMA System Address (SRS00.SAAR or SRS22.DMASA1/SRS23.DMASA2) register defines the base address of the data block. The length of the data transfer is defined by the Block Count (SRS01.BCCT) and Transfer Block Size (SRS01.TBS) values.
There is no limitation on the SDMA System Address register value, the data block can start at any address, and the address does not need to be aligned to any boundary.
The SDMA engine waits at every boundary specified in the SDMA Buffer Boundary (SRS01.SDMABB or U2SDMABB) register.
Once the buffer boundary is reached, the SD host controller stops the current transfer and generates the DMA interrupt. Software needs to update the SDMA System Address register to continue the transfer.
When the SDMA engine stops at the buffer boundary, the SDMA System Address register points to the next system address of the next data position to be transferred. The SDMA engine restarts the transfer when the uppermost byte of the SDMA System Address register is written.
The SDMA engine does not use the ADMA Error Status (SRS21) register.
The figure below shows how the SDMA operates.