Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: ffs1672426695444
Ixiasoft
Visible to Intel only — GUID: ffs1672426695444
Ixiasoft
3.5.3.7. Generic Interrupt Controller CPU Interface
The GIC CPU interface, when integrated with an external distributor component is a resource for supporting and managing interrupts in a cluster system. The GIC CPU interface hosts registers to mask, identify, and control states of interrupts forwarded to that core. There is a separate GIC CPU interface for each core in the system.
- Two security states
- Interrupt virtualization
- Software-generated interrupts
- Message-based interrupts
- System register access for the CPU interface
- Interrupt masking and prioritization
- Cluster environments
- Wake up events in power management environments