Visible to Intel only — GUID: hxs1677112493196
Ixiasoft
Visible to Intel only — GUID: hxs1677112493196
Ixiasoft
2.1. HPS Differences Among Intel SoC Device Families
Feature | Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC, Intel® Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC |
---|---|---|---|---|
Micro Processor Unit (MPU) | Single/Dual Cortex* -A9 | Dual Cortex* -A9 | Quad Cortex* -A53 | Dual Cortex* -A76 and dual Cortex* -A55 with DSU 1 |
Cache Coherency Controller | Accelerator coherency port (ACP) | ACP | Cache Coherency Unit (CCU) | CCU1 |
Generic Interrupt Controller (GIC) | Yes | Yes | Yes | Yes1 |
System Memory Management Unit (SMMU) | No | No | Yes | Yes1 |
On-Chip RAM (OCRAM) | 64 KB | 256 KB | 256 KB | 512 KB1 |
Ethernet Media Access Controller (EMAC) | 2 | 3 | 3 | 31 |
DMA Controller | 1 | 1 | 1 | 21 |
NAND Flash Controller | Yes | Yes | Yes | Yes1 |
SD/eMMC Host Controller | Yes | Yes | Yes | Yes1 |
Combo DLL PHY | No | No | No | Yes1 |
Quad SPI Flash Controller | Yes (inside HPS) | Yes (inside HPS) | No (outside of HPS, uses SDM) | No (outside of HPS, uses SDM) |
USB 3.1 Gen 1 Controller | No | No | No | 11 |
USB 2.0 OTG Controller | 2 | 2 | 2 | 1 |
I3C Controller | No | No | No | 21 |
I2C Controller | 4 | 5 | 5 | 5 |
SPI Controller | 2 masters and 2 slaves | 2 masters and 2 slaves | 2 masters and 2 slaves | 2 masters and 2 slaves |
Timers | 4 | 4 | 4 | 4 |
Watchdog Timers | 2 | 2 | 4 | 5 |
UART Controller | 2 | 2 | 2 | 2 |
Controller Area Network (CAN) Controller | 2 | No | No | No |
General-Purpose I/O Interface (GPIO) | Yes | Yes | Yes | Yes |
Hard Processor System I/O Pin Multiplexing | Dedicated I/O with Loaner capability for Cyclone V SoC: 67 Dedicated I/O with Loaner capability for Arria V SoC: 94 |
Dedicated I/O: 17 Shared I/O: 48 |
Dedicated I/O: 48 Shared I/O: 0 |
Dedicated I/O: 48 Shared I/O: 0 |
System Manager | Yes | Yes | Yes | Yes1 |
Clock Manager | Yes | Yes | Yes | Yes1 |
Reset Manager | Yes | Yes | Yes | Yes1 |
FPGA Manager | Yes | Yes | No (uses SDM) | No (uses SDM) |
Scan Manager | Yes | No | No | No |
Security Manager | No | Yes | No (uses SDM) | No (uses SDM) |
HPS-FPGA Bridges | Yes | Yes | Yes | Yes1 |
SDRAM Controller | Inside HPS | Outside of HPS | Outside of HPS | Outside of HPS1 |
System Interconnect | Yes | Yes | Yes | Yes1 |
Error Checking and Correction (ECC) Controller | No | Yes | Yes | Yes1 |
CoreSight Debug and Trace | Yes | Yes | Yes | Yes1 |
Secure Device Manager (SDM) Interface | No | No | Yes | Yes |
Booting and Configuration | 3 options: HPS Boot and FPGA Configuration occur separately, FPGA Configuration First, HPS Boot First |
3 options: HPS Boot and FPGA Configuration occur separately, FPGA Configuration First, HPS Boot First |
2 options: FPGA Configuration First, HPS Boot First |
2 options: FPGA Configuration First, HPS Boot First |