Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.8.6.5.9.6. I2C Private Write or Read Transfers

The I2C private write and read transfers are initiated on the bus based on the COMMAND_PORT settings as shown in the table below:

Table 256.  I2C Private Write/Read Transfers Required Programming Values
Command Attribute Bit-Field Programmed Value Description
Transfer Command CP 0 Indicates the controller to not consider the CMD field.
CMD[14] NA This field is not applicable since CP bit is set to 0
CMD[13:7] NA This field is not applicable since CP bit is set to 0
DEV_INDX DEV_INDX Indicates the index of the device table which consists of the slave address to be targeted.
SPEED 0 or 1

Indicates the controller that the transfer should go in I2C SDR mode. Values (I2C mode):

  • 0x0: I2C Fm
  • 0x1: I2C Fm+
SDAP 0 or 1
  • 0: Indicates to consider the transmit data from the transmit FIFO if RnW is set to 0.
  • 1: Indicates the controller to consider the transmit data from the command if RnW is set to 0.

RnW (Read and Write)

0 or 1
  • 0: Indicates the transfer is write transfer.
  • 1: Indicates the transfer is read transfer.
PEC 0 or 1

Indicates whether packet error check is enabled for private SDR transfers.

  • 0: PEC check is disabled.
  • 1: PEC check is enabled.

Transfer Argument

(SDAP=0)

DATA_LENGTH 0 - 65535 Indicates the transfer length of the transfer.

Short Data Argument

(SDAP=1)

BYTE_STRB 0,1,3,7 Indicates the respective data bytes of the immediate command are valid.
Note:
  • The LEGACY_I2C_DEVICE bit in the device address table pointed by the DEV_INDX field of the transfer command must be set to 1 for the I2C private transfers.
  • The I3C controller uses the I2C protocol to initiate the I2C transfers for the legacy I2C devices.
  • To allow the priority for the IBI from the I3C devices, the I3C controller can include address header for the I2C private transfers through enabling the IBA_INCLUDE bit in the DEVICE_CTRL register.

The I3C controller halts in case of the following conditions:

  • Receiving NACK for the address header of the private transfers if IBA_INCLUDE bit is enabled in the DEVICE_CTRL register.
  • Receiving NACK for the slave address of the private transfers.

The controller updates the ERR_STS field with appropriate error information in the response status and halts the controller and gives back the control to the application to resume the operation of the controller through writing 1 to the RESUME bit of the DEVICE_CTRL register.