Visible to Intel only — GUID: oum1684439084393
Ixiasoft
Visible to Intel only — GUID: oum1684439084393
Ixiasoft
5.3.6.4.5.3. Cache Commands
The NAND controller supports cache read and program commands in CMD DMA and PIO operation modes.
For devices that support cache read sequence, the cache_rd_en bit in the cache_config (0x0438) register must be set, after this, the controller sequences the multi-page read commands as cache read sequence.
For the devices that support cache program sequences, cache_wr_en bit in the cache_config (0x0438) register must be set, after this, the controller sequences the multi-page program commands as cache write sequence.
Refer to Configure Multiplane and Cache Operations section for more detail about this.