Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

15.6. CoreSight Debug and Trace Programming Model

This section describes programming model details specific to Intel's implementation of the Arm* CoreSight* technology.

The debug components can be configured to cause triggers when certain events occur.

For example, soft logic in the FPGA fabric can signal an event which triggers an STM message injection into the trace stream.

For more information about the programming interface of each Arm* component, refer to the CoreSight* Technical Reference Manual; Chapter 9 Programmers Model.

Related Information

CoreSight SoC-600 Technical Reference Manual