Visible to Intel only — GUID: qfl1679439946833
Ixiasoft
Visible to Intel only — GUID: qfl1679439946833
Ixiasoft
5.8.6.5.9.5. I3C Private Write or Read Transfers
The I3C private write and read transfers are initiated on the bus based on the COMMAND_PORT and settings shown in the table below.
Command Attribute | Bit-Field | Programmed Value | Description |
---|---|---|---|
Transfer Command | CP | 0 | Indicates the controller to not consider the CMD field. |
CMD[14] | NA | This field is not applicable since CP bit is set to 0 | |
CMD[13:7] | NA | This field is not applicable since CP bit is set to 0 | |
DEV_INDX | DEV_INDX | Indicates the index of the device table which consists of the slave address to be targeted. | |
SPEED | 0 to 4 | Indicates the controller that the transfer should go in SDR mode. | |
SDAP | 0 or 1 |
|
|
RnW (Read and Write) |
0 or 1 |
|
|
PEC | 0 or 1 | Indicates whether packet error check is enabled for private SDR transfers.
|
|
Transfer Argument (CMD_ATTR=0) |
DATA_LENGTH | 0 - 65535 | Indicates the transfer length of the transfer. |
Short Data Argument (CMD_ATTR=1) |
BYTE_STRB | 0,1,3,7 | Indicates the respective data bytes of the immediate command are valid. |
- The LEGACY_I2C_DEVICE bit in the device address table pointed by the DEV_INDX field of the transfer command should set to zero for the I3C private transfers.
- To avoid the initial latencies of the transfer, the controller uses TX/RX_START_THLD before initiating the transfer. TX_START_THLD ensures that the threshold level of data is present in the transmit buffer for write transfer and RX_START_THLD level of space is available in the receive buffer for the read transfer before initiating the transfer. This threshold is applicable only for the transfers which are initiated with the START condition and not applicable for the transfers which are initiated with the RESTART condition for SDR transfers.
- To allow the priority for IBI from the devices, the I3C controller can include address header for the I3C private transfers by enabling the IBA_INCLUDE bit in the DEVICE_CTRL register since IBI always wins when arbitrated with address header.
The I3C controller halts in case of the following conditions:
- Receiving NACK for the address header of the private transfers if IBA_INCLUDE bit is enabled in the DEVICE_CTRL register.
- Receiving NACK for the slave address of the private transfers.
The controller updates the ERR_STS field with appropriate error information in the response status and halts the controller and gives back the control to the application to resume the operation of the controller through writing ‘1’ to the Resume bit of the DEVICE_CTRL register.