Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

15.5.1.4.3. Debug Reset Limitation

Due to a limitation in the HPS, the debug reset is unable to reset the Arm* cluster debug logic via the nPRESET and nATRESET cluster reset inputs. Because of this, the Arm* cluster nPRESET and nATRESET inputs are connected to the functional L2 reset, and the DSU DebugBlock nPRESET is connected to the debug reset. This means that the debug reset resets all CoreSight* debug and trace system (including the DSU Debug Block) outside of the Arm* DSU cluster, but does not reset the debug and trace system within the Arm* DSU cluster (ETMs, CTIs, Cortex-A76/Cortex-A55 debug registers). If the Arm* DSU cluster debug IP is not working properly, then a cold reset or power-on reset is required. Otherwise, the debug reset should be sufficient to reset all other CoreSight* debug and trace system infrastructure.

Note: The new CoreSight* SoC-600 APB system no longer supports PADDRDBG31 and adapters are provided for older debug systems. This includes the STM and the DSU. For the FPGA fabric debug APB connection, the PADDRDBG31 interface signal remains, but is tied to 1’b1 to indicate the access is from an external debugger. In other words, there is no way to differentiate between an external debugger or internal debug monitor access to soft IP in the FPGA fabric.