Visible to Intel only — GUID: bea1679133676677
Ixiasoft
Visible to Intel only — GUID: bea1679133676677
Ixiasoft
14.6.6.1. Single-Bit Error Interrupts
The Single-Bit Error Interrupt Enable (ERRINTEN) register must be configured for single-bit error interrupt generation.
For true dual port memory, a separate interrupt is generated for errors on each memory port.
The ECC controller can generate a single-bit error interrupt for:
- All single-bit errors
- LUT overflow
- Single-bit error counter match
The address of the most recent single-bit error is logged in the Single-Bit Error Address (SERRADDRx) register.
Single-bit errors that occur during a read-modify-write cycle for a sub-word access are flagged in the MODSTAT register in addition to triggering an interrupt.
The interrupt status (INSTAT) register indicates if a single-bit error is pending in the ECC controller. All single-bit interrupts are cleared by clearing the single-bit error pending bit of the INTSTAT register. The single-bit interrupt generation can be disabled by setting the error interrupt reset bit of the Error Interrupt Reset (ERRINTENR) register.