Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.6.2. Initialization Protocol (Device Discovery)

You must configure the NAND Flash controller according to the type and characteristics of the NAND Flash device you are connecting. To do this, you can use the device discovery mechanism which is supported by the NAND Flash controller. The device discovery mechanism is an initialization protocol that automatically detects what kind of Flash device is connected and minimally configures the controller to perform simple data transfers (disabling ECC, cache, multiplane, and multi-LUN operations and setting timing parameters to the maximum values).

During the device discovery process, the controller classifies the NAND Flash device using the categories shown in the following table.

Table 181.  Device Discovery Initialization Categories
Type of Device Details
ONFI Support Read ID (with address 0x20 and 0x00), READ PARAMETER PAGE, and CHANGE READ Column with 2 address bytes commands.
Toggle

Support Read ID (with address 0x40 and 0x00), READ PARAMETER PAGE and CHANGE READ Column with 2 address bytes commands. The NAND Flash controller can handle memories with both 256 bytes and 512 bytes parameter page. When this mode is detected, the controller automatically switches PHY logic to utilize values provided in the phy_*_reg signals (see Device Discovery interface in 4.3.5 Signals Description section).

The following signals in the system manager must be set with the appropriate value. See the description of the PHY registers in the NAND Flash Controller Programming Model section.

phy_ctrl_reg phy_dqs_timing_reg phy_dll_slave_ctrl_reg
phy_tsel_reg phy_gate_lpbk_ctrl_reg
phy_dq_timing_reg phy_dll_master_ctrl_reg
Legacy

Support for READ ID command with address 0x00 is required. Only a few predefined memory types are supported. Additionally, the dd_* signals are used to fetch information missing in READ ID command (see Device Discovery Interface).

Unrecognized

In case of unrecognized devices, the controller uses the dd_* signals to read required configuration (see the Device Discovery Interface section).

The controller outputs the value returned by NAND Flash device on READ ID command with address 0x00 on the dd_id_value signal together with asserting the dd_req signal. Then it expects logical 1 on the dd_ack signal asserted together with values of page size (dd_page_size signal), number of pages per block (dd_pages_per_block), field selecting the number of the row address bytes (dd_row_addr_width), flag selecting the 16 bit DQ bus on the Flash interface (dd_support_16_bit_en), number of LUN-es in single NAND Flash device (dd_lun_number).

Note: For the devices that start working in DDR modes (NV-DDR or Toggle Mode), the nf_clk clock frequency must be consistent with the timing mode requirement in which the devices started work.

The device discovery process can be divided into the following phases:

  • Phase 1: Waiting for NAND flash device to be ready after power-on. The controller waits for RB_valid_Vcc time (from NAND flash device specification) which is defined with rb_valid_time signal. After this time, the controller checks for dfi_rbn[0] signal (in DFI interface) and waits until it will be set to 1. This indicates that the NAND flash memory device is ready for the next phase of initialization process.
  • Phase 2: Sending RESET command (0xFF) to the NAND Flash memory device and waiting to finish processing this command. After this, if the discovery_inhibit signal is set to 1, the controller is configured with values provided on the dd_* signals and the initialization process is finished. Otherwise, the next phase is executed.
  • Phase 3: Detecting memory type with READ ID command.
    1. The controller sends the READ ID command with the 0x20 address and tries to read the ONFI signature.
    2. If the signature is not correct it sends the READ ID command with 0x40 address to detect the JEDEC signature.
    3. If the signature is still not correct, the controller sends the READ ID command with the 0x00 address to detect legacy device.
    4. If the signature is still unknown, the controller classifies the connected devices as “unrecognized device”

    A RESET command is sent between each one of the READ ID commands to ensure that NAND Flash memory device is not in a unknown state.

  • Phase 4: Reading NAND Flash device parameters and setting control registers of the controller.

    Depending on the device type classification in the previous phase, the controller reads NAND Flash memory parameters value based on:

    • Value of READ ID command with 0x00 address for all types of devices.
    • Value of Parameter page for ONFI and Toggle devices only.
    • Values provided on dd_* signals for unrecognized devices.
Note: If discovery_ignore_crc signal is cleared, the controller checks the CRC value in the parameters page. If this check fails, the controller will read the next copy of the parameters page (up to 3 copies).
Note: If toggle device is detected, the controller automatically switches the PHY logic to toggle mode before this phase.
Note: For legacy devices, the controller uses the dd_* interface to get information about LUN number and number of row address cycles (dd_lun_number and dd_row_addr_width).

When the initialization finishes, the controller will indicate this asserting the init_comp output signal and setting the init_comp bit in ctrl_status(0x0118) register.

If the device discovery mechanism finishes with a failure, the NAND Flash controller sets a value of 0x0 to the dd_id_value signal along with the assertion of the dd_req signal. Then the controller will expect a logical 1 on the dd_ack pin which should be asserted along with the default values set in the dd_page_size, dd_pages_per_block, dd_row_addr_width, dd_support_16_bit_en, and dd_lun_number signals coming from the system manager.

The minimum configuration required by the controller to perform any transfer operation is shown in the following table.

Table 182.  Required Minimum Configuration for Transfer Operation
Register in NAND Flash Controller Field in Register
transfer_cfg_1 (0x0404) Set value of sector_size and last_sector_size fields that define the size of the main area in a NAND Flash page.
nf_dev_layout (0x0424) Set the value of PPB (pages per block) in the NAND Flash device.
device_ctrl (0x0430) Set value of row_addr_width field to select the number of row address bytes supported in the NAND Flash device.
common_settings (0x1008) Set value in device_16bit field for 16-bit NAND Flash devices.

If the device discovery mechanism is disabled (with discovery_inhibit signal set to 1), the host must program the previous registers before executing any NAND command.

Additionally to the configuration provided by the device discovery mechanism under success scenario, the controller may fill the reset of the registers described in the following table. The following table also describes how the register fields are obtained.

Note:

Use this key to understand the fields in the table.

  • ID: Value obtained with the READ ID command.
  • PP: Value obtained with the READ PARAMETER PAGE command.
  • SysMgr: System manager signals in the device discovery interface.
  • X: Value not available for this type of memory.
Table 183.  Additional Configuration Required after Device Discovery
Register Name ONFI Toggle Legacy Unrecognized

transfer_cfg_1 (0x0404)

PP PP ID SysMgr
nf_dev_layout (0x0424) PP – Only PPB and LN fields PP – Only PPB and LN fields ID, SysMgr - Only PPB and LN fields SysMgr - Only PPB and LN fields
device_ctrl (0x0430) PP – Only row_addr_width field PP – Only row_addr_width field SysMgr - Only row_addr_width field SysMgr - Only row_addr_width field
common_settings (0x1008) PP – Only device_16bit field PP – Only device_16bit field ID – Only device_16bit field SysMgr – Only device_16bit field
manufacturer_id (0x0808) ID ID ID ID
nf_device_areas (0x080c) PP PP

ID -spare_area_size not available

SysMgr - spare_area_size not available

device_params_0 (0x0810) ID and PP ID and PP

ID – only device_type available

ID and SysMgr - plane_addr_bits and bits_per_cell not available

device_params_1 (0x0814) ID ID X X
device_features (0x0818) PP PP X X
device_blocks_per_lun (0x081c) PP PP X X
device_revision (0x0820) PP PP X X
onfi_timing_modes_0 (0x0824) PP X X X
onfi_timing_modes_1 (0x0828) PP X X X
onfi_iterlv_op_attr (0x082c) PP X X X
onfi_sync_opt_0 (0x0830) PP X X X
onfi_sync_opt_1 (0x0834) PP X X X