Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

6.4.3. ECC and Parity Control

The system manager can mask the ECC interrupts from each of the following HPS modules with ECC-protected RAM:

  • MPU L2 cache data RAM
  • On-chip RAM
  • USB 2.0 OTG controller (USB0) RAM
  • USB 3.1 controller (USB1) RAM
  • EMAC (EMAC0, EMAC1, and EMAC2) RAM

System manager provides combined ECC status and interrupt from each of these HPS modules. Each modules generates single or double bit error, which the system manager combines to generate interrupts.

Single bit ECC errors are maskable at system manager level by using the ecc_intmask register. Double bit errors are non-maskable.

ECC interrupt status is captured in the system manager register, which has the accessibility as RO (read only). Therefore, you need to clear the status at the actual source of the interrupt to release it.