Visible to Intel only — GUID: ljs1673292725227
Ixiasoft
Visible to Intel only — GUID: ljs1673292725227
Ixiasoft
12.2.6.3. AxUSER Bit Connectivity
The F2H and F2SDRAM ports support read and write stream IDs (SID) and secure state determination (SSD) signals as a hint to the respective TBU as to what translations must be performed for the current transactions. The FlexNoC does not directly support these signals as part of the AXI protocol, therefore they must be transported through the MPFE NoC as AxUSER signals.
The MPFE NoC supports masterID based firewalls to grant access to regions of SDRAM by both the FPGA fabric and HPS masters. Therefore, the AxUSER signals from the CCU must also be brought into the MPFE NoC.
By convention, accesses from F2SDRAM:
- AxUSER[7:0] must be set to 0xE0
- AxUSER[8] = 1, then AxPROT settings are used to determine security
- AxUSER[8] = 0, then AxPROT settings are overridden, and transactions are non-secure
By convention, accesses from F2H:
- AxUSER[7:0] = 0x04