Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

12.2.5.2. IOBank Introduction

This section provides a brief overview of the IOBank block.

Note: In this chapter, “IOBank” is used as a generic term that refers to the block that contains the specific/dedicated IO pins and Hard Memory Controller required for SDRAM connected to the MPFE. In various other collaterals and tools, such as Quartus® Prime, Simics, U-Boot software, HPS register maps, and so on, the IOBank can also be called “IO96B” or “HPS Shared GPIO Bank” or “HPS Shared HSIO Bank”.
Note: For Agilex™ 5 E-series and D-series, IOBank_0 is IO Bank 3A and IOBank_1 is IO Bank 3B.

The IOBank is the subsystem which houses the high-speed IO. It supports DDR, differential (LVDS + MIPI d-phy), and GPIO applications. Each I/O bank contains 96 general purpose I/Os and two high-efficiency hard memory controllers. The hard memory controllers support various memory types, each with different performance capabilities. You can bypass the hard memory controller and implement a soft memory controller in user logic.

Figure 293. IOBank Block Diagram