Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.4.6.3.2. ADMA2 Operation

The Advanced DMA Mode Version 2 (ADMA2) uses the descriptors list to describe data transfers. The SD host registers only define the base address of the descriptors list. The base addresses and sizes of the data pages are defined inside the descriptors.

The controller supports ADMA2 in 64-bit or 32-bit addressing mode.

When in ADMA2 mode, the SD host transfers data from data pages. A page is a block of valid data defined by a single ADMA2 descriptor. Each ADMA2 descriptor can define only one data page. The starting address of the data page must by aligned to a 4-byte boundary in 32-bit addressing mode, and to an 8-byte boundary in 64-bit addressing mode. The size of each data page is arbitrary, and it depends on neither the previous nor the successive page size. It can also be different from the SD card transfer block size (SRS01.TBS).

The ADMA2 engine transfers are configured in a descriptor list. The base address of the list is set in the ADMA System Address register (SRS22.DMASA1, SRS23.DMASA2), regardless of whether it is a read or write transfer. The ADMA2 descriptor list consists of several descriptors of distinct functions. Each descriptor provides the following functionality:

  • Performs transfer of data page of specified size
  • Links next descriptor address to an arbitrary memory location
  • Contains the following flags:
    • VAL – Denotes a valid ADMA descriptor
    • END – Denotes the last descriptor of the descriptor list
    • INT – Denotes the ADMA interrupt request when the current descriptor action is complete

The following figure shows the ADMA2 descriptor layout.

Figure 141. ADMA2 Descriptor Layout
The following table describes the ADMA2 descriptor fields.
Table 219.  ADMA2 Descriptor Fields
Bit Symbol Description

[95:32]

[63:32]

ADDRESS The field contains data page address or next descriptor list address depending on the descriptor type. When the descriptor is type TRAN, the field contains the page address. When the descriptor type is LINK, the field contains the address for the next descriptor list.
[31..16] LENGTH The field contains data page length in bytes. If this field is 0, the page length is 64 kBytes.
[5:4] ACT

The field defines the type of descriptor.

  • 2’b00 (NOP): no operation, go to next descriptor in the list
  • 2’b01 (Reserved): behavior identical to NOP
  • 2’b10 (TRAN): transfer data from the pointed page and go to the next descriptor on the list
  • 2’b11 (LINK): go to the next descriptor list pointed by ADDRESS field of this descriptor
2 INT When this bit is set, the DMA Interrupt (SRS12.DMAINT) is generated when the ADMA2 engine completes processing of the descriptor.
1 END When this bit is set, it signals termination of the transfer and generates a transfer complete interrupt when this transfer is completed.
0 VAL When this bit is set, it indicates the valid descriptor on a list. When this bit is cleared, the ADMA error interrupt is generated and the ADMA2 engine stops processing the descriptor list. This bit prevents ADMA2 engine runaway due to improper descriptors.

The figure below shows how the ADMA2 operates.

Figure 142. ADMA2 Operation