Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.6.1.3. Descriptor Cache Memory

Descriptor cache memory is an external SPRAM. The XGMAC uses the descriptor memory interface (DMI) to read and write the pre-fetched descriptors of all the DMA activities into the descriptor cache memory.

The descriptor cache memory size is 4 KB and the memory is internally stored per the data width, which is 8 bytes (64 bits). 4096 bytes x 1 B memory is physically stored as 512 x 8 B memory which results in 9 bits of address width.

Descriptor cache memory is synchronous to the application clock (aclk_i).