Visible to Intel only — GUID: kzx1672793117221
Ixiasoft
Visible to Intel only — GUID: kzx1672793117221
Ixiasoft
3.7.2. System Integration of the Arm* DynamIQ Shared Unit
- A module which includes the core and the DSU
- The DebugBlock
- CPU bridges
- Snoop control unit (SCU)
- Clock and power management
- L3 memory system
- DSU system control registers
- Debug and trace
Component | Description |
---|---|
CPU bridges | The CPU bridges control buffering and synchronization between the cores and DSU. |
Snoop Control Unit (SCU) | The SCU maintains coherency between all the data caches in the cluster. The SCU contains buffers that can handle direct cache-to-cache transfers between cores without having to read or write data to the L3 cache. Cache line migration enables dirty cache lines to be moved between cores. |
Clock and power management | The cluster supports a set of power saving modes that are controlled by an external power controller. |
L3 memory system | Main memory requester - The main memory interface supports 256-bit AMBA 5 CHI requester interface. Peripheral port - The peripheral port is an optional manager interface and provides device access to tightly coupled accelerators. The port implements a 64-bit AXI 4 manager interface protocol. The peripheral port can be used for low-latency access to peripherals local to the cluster. It has the same latency as the main requester port. However, the overall system latency to devices that are connected to the main requester port is greater because of the higher latency of the system interconnect L3 cache is implemented as 2MB. |
DSU system control registers | The DSU implements a set of system control registers that provide:
|
Debug and trace | Each core includes an Embedded Trace Macrocell (ETM) to allow program tracing while debugging. Trigger events from the cores are combined and output to the Debug APB requester. Trigger events to the cores, and debug register accesses, are received on the Debug APB completer. |