Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.6.4. USB 3.1 Gen1 Controller System Integration

Figure 168. System Integration

The USB 3.1 controller connects to the layer 3 (L3) interconnect through an L4 subordinate bus interface, allowing other managers to access the control and status registers (CSRs) in the controller. The controller also connects to the L3 interconnect through the I/O translation buffer unit (TBU), allowing the DMA engine in the controller to move data between external memory and the controller.

Three two-port Static RAMs (SRAM) are connected to the USB 3.1 controller to store USB data packets for both host and device modes. The two-port RAM means that port1 is read only while port2 is write only. It is configured as FIFO buffers for receive and transmit data packets on the USB link.

Through the system manager, the USB 3.1 controller has control to use and test error correction codes (ECCs) in the RAM wrapper. Through the system manager, the USB 3.1 controller can also control the behavior of the manager interface to the L3 interconnect.