Visible to Intel only — GUID: tcc1677614057476
Ixiasoft
Visible to Intel only — GUID: tcc1677614057476
Ixiasoft
4.1.5.1.4. Distributed Memory Interface (DMI)
A DMI provides an AXI initiator interface to normal memory for coherent and noncoherent transactions. Two DMI are implemented to improve the overall throughput of the memory subsystem. Each DMI supports a 32 Kbyte system memory cache (SMC) to enable CHI-B atomic operations. These ports have medium to high bandwidth requirements.
For each DMI, the following counter is implemented:
- RB message counter
For each DMI, the following resources are implemented based on message credits:
- CMD message skid buffer which is sized based on CMD message credits
- MRD message skid buffer which is sized based on MRD message credits
- RB control entries which are sized based on RB message credits for both DCE and DMI
For each DMI, the following additional resources are implemented:
- Read transaction table control entries which limit the number of read transactions each DMI can have outstanding on the AXI interface
- Write transaction table control entries which limit the number of write transactions each DMI can have outstanding on the AXI interface