Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

11.8.3.4. FPGA-to-HPS CCU to Peripherals (Device Non-Bufferable)

If your logic issues a device non-bufferable transaction, write responses and read data are obtained from the final destination. Reads are not prefetched and writes are not merged. All transactions are non-modifiable, which means each transaction does not split into multiple transactions or merge with other transactions. All transactions from the same ID remain ordered.

For reads, cache is not looked up. Read data is returned directly from peripheral. The following table shows the read data attribute list.

Table 351.  Read Data Attribute List
Attribute Value Note
ARDOMAIN[1:0] ‘b01

Inner sharable

ARBAR[1:0] ‘b00

Normal access, respecting barriers

ARSNOOP[3:0] ‘b0000

ReadOnce

ARCACHE[3:0] ‘b0000

Device non-bufferable

AxUSER[7:0] ‘b00000100

0x04 = CCU

AxPROT[2:0] ‘b001

Data access. Secure access. Privileged access.

AxLEN[7:0]

-

The burst length for:

  • WRAP burst type must be 1, 2, 4, 8, or 16 transfers.
  • INCR burst type is 1 to 256 transfers.
AxSIZE[2:0] -

The number of bytes in a transfer must be equal to the data bus width.

AxBURST[1:0] ‘b01 or ‘b10

Must be INCR(‘b01) or WRAP(‘b10)

AxLOCK[1:0] ‘b00

Must be normal access

AxQOS -

Do not care

For writes, cache is not looked up. Write data is stored directly to peripheral. The following table shows the write data attribute list.

Table 352.  Write Data Attribute List
Attribute Value Note
AWDOMAIN[1:0] ‘b01

Inner sharable

AWBAR[1:0] ‘b00

Normal access, respecting barriers

AWSNOOP[2:0] ‘b000

WriteUnique (could be ‘b001 for WriteLineUnique)

AWCACHE[3:0] ‘b0000

Device non-bufferable

AxUSER[7:0] ‘b00000100

0x04 = CCU

AxPROT[2:0] ‘b001

Data access. Secure access. Privileged access.

AxLEN[7:0]

-

The burst length for:

  • WRAP burst type must be 1, 2, 4, 8, or 16 transfers.
  • INCR burst type is 1 to 256 transfers.
AxSIZE[2:0] -

The number of bytes in a transfer must be equal to the data bus width.

AxBURST[1:0] ‘b01 or ‘b10

Must be INCR(‘b01) or WRAP(‘b10)

AxLOCK[1:0] ‘b00

Must be normal access

AxQOS -

Do not care