Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.8.6.5.9.1. Single Data Rate (SDR) Transfers in Master Mode

In SDR mode, single bit is sent on each SCL clock. All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the master sends the address and R/W bit, the slave receiver must respond to the acknowledge signal (ACK). When a slave-receiver does not respond with an ACK pulse, the master aborts the transfer by issuing a STOP condition. The slave must leave the SDA line high, so that the master can abort the transfer.

The single data rate transfers are initiated by the application through the command as explained in Master Command Data Structures. Based on the command initiated by the application and device address pointed by the DEV_INDX field initiates command, the I3C controller initiates the transfers on the bus. The following table shows the decoded transfer type based on transfer command and device address table.

Table 252.  Broadcast CCC Write Transfer Required Programming Values
Transfer Command

(Command Port)

Device Address Table Decoded Transfer Type
CP CMD[14] SPEED RnW DEVICE
0 NA 0 to 4 0 0 I3C Private write transfer
0 NA 0 to 4 1 0 I3C Private read transfer
1 0 0 to 4 0 0 I3C Broadcast CCC write transfer
1 1 0 to 4 0 0 I3C Directed CCC write transfer
1 1 0 to 4 1 0 I3C Directed CCC read transfer
0 x 0 to 1 0 1 I2C Private write transfer
0 x 0 to 1 1 1 I2C Private read transfer
Others Illegal combination