Visible to Intel only — GUID: dza1679976477141
Ixiasoft
Visible to Intel only — GUID: dza1679976477141
Ixiasoft
14.6.5.3. Single-Bit Error Look-Up Table
The ECC controller of each memory port has a look-up table (LUT) that logs the memory addresses of all unique single-bit error occurrences. Repeated errors at the same memory address are not stored. The LUT keeps track of single-bit errors, but not double-bit errors.
The most significant bit (MSB) of each entry in the LUT is the valid bit. Whenever a single-bit error occurs and is logged by the LUT, the valid bit is set. The rest of the bits in a single LUT entry contain the memory address of the data error. After the memory address has been read from the LUT, software can clear the entry by writing a 1 to the valid bit in the entry. If all of the LUT entries are occupied and valid bits have not been cleared, overflow occurs on the next single-bit error. An interrupt can be generated on a LUT overflow. For more information about interrupts, refer to the ECC Controller Interrupts section.
Peripheral |
LUT Depth (entries) |
---|---|
On-chip RAM |
16 |
USB |
4 |
Ethernet MAC (Rx FIFO) |
4 |
Ethernet MAC (Tx FIFO) |
4 |
The ECC controller register map contains the LUT entries. Software can read the LUT error address and clear the valid bits. For more information, refer to the ECC Controller Address Map and Register Description section.