Visible to Intel only — GUID: slk1674596170386
Ixiasoft
Visible to Intel only — GUID: slk1674596170386
Ixiasoft
7.6.2. MPU/DSU and APS/CCU Clock Groups
The MPU clock group includes the A76 cores (core3_clk, core2_clk), A55 cores (core1_clk, core0_clk), and DSU clocks (SCLK, PCLK, PERIPHCLK). There is no fixed frequency relationship among these cores; you can select any frequency that can be generated by the PLLs and ping-pong counters that are implemented. Since the DSU handles clock domain crossing, there is no required synchronous relationship among the clocks in this group.
Each A76 core has a ping-pong counter so that the performance of each core can be independently configured based on the needs of the application. The two A55 cores share a common ping-pong counter but have independent clock gates, allowing you to disable clocks if an A55 core is not used in your application. The DSU and APS clocks are generated from a single ping-pong counter since they share a common base frequency.
The following figure shows the block diagram for the MPU and APS clock trees.
The following table shows the registers used to program the clocks.
Clock Name | *.src | *.cnt (n+1 divider) | *.div (2^n divider) | Clock Gate (enable) |
---|---|---|---|---|
core3_clk | ctlgrp.core23ctr.src = 0 (Main_PLL_C0) = 1 (Peri_PLL) |
ctlgrp.core3ctr.cnt | --- | mainpllgrp.en.core3en |
core2_clk | ctlgrp.core2ctr.cnt | --- | mainpllgrp.en.core2en | |
core1_clk | ctlgrp.core01ctr.src = 0 (Main_PLL_C1) = 1 (Peri_PLL_C0) |
ctlgrp.core01ctr.cnt | --- | mainpllgrp.en.core1en |
core0_clk | mainpllgrp.en.core0en | |||
mpu_free_clk | ctlgrp.dsuctr.src = 0 (Main_PLL_C2) = 1 (Peri_PLL_C0) |
ctlgrp.dsuctr.cnt | --- | --- |
mpu_clk | --- | --- | ||
mpu_ccu_clk | mainpllgrp.nocdiv.ccudiv | --- | ||
mpu_periph_clk | mainpllgrp.nocdiv.mpuperiphdiv | --- |