Visible to Intel only — GUID: btp1674596579916
Ixiasoft
Visible to Intel only — GUID: btp1674596579916
Ixiasoft
7.6.8. H2F User Clock Group
The H2F clocks are generated in the HPS and provided to the FPGA. These clocks connect to the FPGA fabric using the GCLKs, RCLKs, and PCLKs:
- Global clock (GCLK): These clocks use global routing resources in the FPGA.
- Regional clock (RCLK): These clocks route only to part of the chip, for example the entire FPGA width and height of I/O tiles.
- Periphery clock (PCLK): These clocks are for high speed I/O interfaces.
The following diagram shows the H2F user clock group.
The following table shows the clock information for the H2F user clock group.
Clock Name | HPS Clock Source | Clock Destination | Description |
---|---|---|---|
h2f_user0_clk | Clock manager | FPGA LE | General purpose use |
h2f_user1_clk | Clock manager | FPGA LE | General purpose use |
tpiu_trace_clk_hio, tpiu_trace_clk_div2 |
TPIU | FPGA LE -> Pin | Trace clock generated by TPIU, ½ of tpiu_trace_clkin. Also duplicated output on FPGA interface left. |
emac0_phy_txclk_o_hio | EMAC 0 | FPGA LE -> Pin | Transmit clock for EMAC 0 when FPGA interface is used instead of HPS I/O pins |
emac1_phy_txclk_o_hio | EMAC 1 | FPGA LE -> Pin | Transmit clock for EMAC 1 when FPGA interface is used instead of HPS I/O pins |
emac2_phy_txclk_o_hio | EMAC 2 | FPGA LE -> Pin | Transmit clock for EMAC 2 when FPGA interface is used instead of HPS I/O pins |
The following table shows the registers used to program the clocks.
Clock Name | *.src | *.cnt (n+1 divider) | *.div (2^n divider) | Clock Gate (enable) |
---|---|---|---|---|
h2f_user0_clk | ctlgrp.s2fuser0ctr.src = 0 (Main_PLL_C1) = 1 (Peri_PLL_C3) |
ctlgrp.s2fuser0ctr.cnt | --- | mainpllgrp.en.s2fuser0clken |
h2f_user1_clk | ctlgrp.s2fuser1ctr = 0 (Main_PLL_C1) = 1 (Peri_PLL_C3) |
ctlgrp.s2fuser1ctr.cnt | --- | perpllgrp.en.s2fuser1clken |